clk/rockchip/clk_rk3568.c

68 	[APLL] = PLL(pll_rk3328, PLL_APLL, RK3568_PLL_CON(0),
581 	old_rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL],  in rk3568_armclk_set_clk()
582 					 priv->cru, APLL);  in rk3568_armclk_set_clk()
584 		if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],  in rk3568_armclk_set_clk()
585 					  priv->cru, APLL, hz))  in rk3568_armclk_set_clk()
612 		if (rockchip_pll_set_rate(&rk3568_pll_clks[APLL],  in rk3568_armclk_set_clk()
613 					  priv->cru, APLL, hz))  in rk3568_armclk_set_clk()
2530 		rate = rockchip_pll_get_rate(&rk3568_pll_clks[APLL], priv->cru,  in rk3568_clk_get_rate()
2531 					     APLL);  in rk3568_clk_get_rate()
3257 			rockchip_pll_get_rate(&rk3568_pll_clks[APLL],  in rk3568_clk_init()
3258 					      priv->cru, APLL);  in rk3568_clk_init()