Lines Matching full:else
296 else in rk3568_pwm_get_pmuclk()
320 } else { in rk3568_pwm_set_pmuclk()
346 else in rk3568_pmu_get_pmuclk()
465 else in rk3568_rtc32k_set_parent()
526 } else { in rk3568_pmuclk_bind()
599 } else if (old_rate < hz) { in rk3568_armclk_set_clk()
729 else in rk3568_cpll_div_set_rate()
747 else if (sel == ACLK_BUS_SEL_150M) in rk3568_bus_get_clk()
749 else if (sel == ACLK_BUS_SEL_100M) in rk3568_bus_get_clk()
751 else in rk3568_bus_get_clk()
760 else if (sel == PCLK_BUS_SEL_75M) in rk3568_bus_get_clk()
762 else if (sel == PCLK_BUS_SEL_50M) in rk3568_bus_get_clk()
764 else in rk3568_bus_get_clk()
784 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
786 else if (rate == 100 * MHz) in rk3568_bus_set_clk()
788 else in rk3568_bus_set_clk()
798 else if (rate == 75 * MHz) in rk3568_bus_set_clk()
800 else if (rate == 50 * MHz) in rk3568_bus_set_clk()
802 else in rk3568_bus_set_clk()
828 else if (sel == ACLK_PERIMID_SEL_200M) in rk3568_perimid_get_clk()
830 else if (sel == ACLK_PERIMID_SEL_100M) in rk3568_perimid_get_clk()
832 else in rk3568_perimid_get_clk()
840 else if (sel == HCLK_PERIMID_SEL_100M) in rk3568_perimid_get_clk()
842 else if (sel == HCLK_PERIMID_SEL_75M) in rk3568_perimid_get_clk()
844 else in rk3568_perimid_get_clk()
864 else if (rate == 200 * MHz) in rk3568_perimid_set_clk()
866 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
868 else in rk3568_perimid_set_clk()
877 else if (rate == 100 * MHz) in rk3568_perimid_set_clk()
879 else if (rate == 75 * MHz) in rk3568_perimid_set_clk()
881 else in rk3568_perimid_set_clk()
907 else if (sel == ACLK_TOP_HIGH_SEL_400M) in rk3568_top_get_clk()
909 else if (sel == ACLK_TOP_HIGH_SEL_300M) in rk3568_top_get_clk()
911 else in rk3568_top_get_clk()
919 else if (sel == ACLK_TOP_LOW_SEL_300M) in rk3568_top_get_clk()
921 else if (sel == ACLK_TOP_LOW_SEL_200M) in rk3568_top_get_clk()
923 else in rk3568_top_get_clk()
931 else if (sel == HCLK_TOP_SEL_100M) in rk3568_top_get_clk()
933 else if (sel == HCLK_TOP_SEL_75M) in rk3568_top_get_clk()
935 else in rk3568_top_get_clk()
943 else if (sel == PCLK_TOP_SEL_75M) in rk3568_top_get_clk()
945 else if (sel == PCLK_TOP_SEL_50M) in rk3568_top_get_clk()
947 else in rk3568_top_get_clk()
967 else if (rate == 400 * MHz) in rk3568_top_set_clk()
969 else if (rate == 300 * MHz) in rk3568_top_set_clk()
971 else in rk3568_top_set_clk()
980 else if (rate == 300 * MHz) in rk3568_top_set_clk()
982 else if (rate == 200 * MHz) in rk3568_top_set_clk()
984 else in rk3568_top_set_clk()
993 else if (rate == 100 * MHz) in rk3568_top_set_clk()
995 else if (rate == 75 * MHz) in rk3568_top_set_clk()
997 else in rk3568_top_set_clk()
1006 else if (rate == 75 * MHz) in rk3568_top_set_clk()
1008 else if (rate == 50 * MHz) in rk3568_top_set_clk()
1010 else in rk3568_top_set_clk()
1041 else if (sel == CLK_I2C_SEL_100M) in rk3568_i2c_get_clk()
1043 else if (sel == CLK_I2C_SEL_CPLL_100M) in rk3568_i2c_get_clk()
1045 else in rk3568_i2c_get_clk()
1063 else if (rate == 100 * MHz) in rk3568_i2c_set_clk()
1065 else in rk3568_i2c_set_clk()
1128 else if (rate == 100 * MHz) in rk3568_spi_set_clk()
1130 else in rk3568_spi_set_clk()
1202 else in rk3568_pwm_set_clk()
1244 else in rk3568_adc_get_clk()
1278 } else { in rk3568_adc_set_clk()
1317 else if (sel == ACLK_SECURE_FLASH_SEL_150M) in rk3568_crypto_get_rate()
1319 else if (sel == ACLK_SECURE_FLASH_SEL_100M) in rk3568_crypto_get_rate()
1321 else in rk3568_crypto_get_rate()
1331 else if (sel == HCLK_SECURE_FLASH_SEL_100M) in rk3568_crypto_get_rate()
1333 else if (sel == HCLK_SECURE_FLASH_SEL_75M) in rk3568_crypto_get_rate()
1335 else in rk3568_crypto_get_rate()
1343 else if (sel == CLK_CRYPTO_CORE_SEL_150M) in rk3568_crypto_get_rate()
1345 else in rk3568_crypto_get_rate()
1353 else if (sel == CLK_CRYPTO_PKA_SEL_200M) in rk3568_crypto_get_rate()
1355 else in rk3568_crypto_get_rate()
1375 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1377 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1379 else in rk3568_crypto_set_rate()
1389 else if (rate == 100 * MHz) in rk3568_crypto_set_rate()
1391 else if (rate == 75 * MHz) in rk3568_crypto_set_rate()
1393 else in rk3568_crypto_set_rate()
1401 else if (rate == 150 * MHz) in rk3568_crypto_set_rate()
1403 else in rk3568_crypto_set_rate()
1411 else if (rate == 200 * MHz) in rk3568_crypto_set_rate()
1413 else in rk3568_crypto_set_rate()
1750 else if (sel == ACLK_VOP_PRE_SEL_CPLL) in rk3568_aclk_vop_get_clk()
1752 else if (sel == ACLK_VOP_PRE_SEL_VPLL) in rk3568_aclk_vop_get_clk()
1754 else in rk3568_aclk_vop_get_clk()
1768 } else { in rk3568_aclk_vop_set_clk()
1805 else if (sel == DCLK_VOP_SEL_VPLL) in rk3568_dclk_vop_get_clk()
1808 else if (sel == DCLK_VOP_SEL_GPLL) in rk3568_dclk_vop_get_clk()
1810 else if (sel == DCLK_VOP_SEL_CPLL) in rk3568_dclk_vop_get_clk()
1812 else in rk3568_dclk_vop_get_clk()
1851 } else if (sel == DCLK_VOP_SEL_VPLL) { in rk3568_dclk_vop_set_clk()
1861 } else { in rk3568_dclk_vop_set_clk()
1896 } else { in rk3568_dclk_vop_set_clk()
2072 else if (rate == 25000000) in rk3568_gmac_tx_rx_set_clk()
2074 else in rk3568_gmac_tx_rx_set_clk()
2079 } else if (sel == RMII0_MODE_SEL_RMII) { in rk3568_gmac_tx_rx_set_clk()
2082 else in rk3568_gmac_tx_rx_set_clk()
2145 else in rk3568_rkvdec_get_clk()
2156 else if (src == CLK_RKVDEC_CORE_SEL_NPLL) in rk3568_rkvdec_get_clk()
2158 else if (src == CLK_RKVDEC_CORE_SEL_VPLL) in rk3568_rkvdec_get_clk()
2160 else in rk3568_rkvdec_get_clk()
2181 else in rk3568_rkvdec_set_clk()
2196 else if (src == CLK_RKVDEC_CORE_SEL_NPLL) in rk3568_rkvdec_set_clk()
2198 else if (src == CLK_RKVDEC_CORE_SEL_VPLL) in rk3568_rkvdec_set_clk()
2200 else in rk3568_rkvdec_set_clk()
2261 else if (p_src == CLK_UART_SRC_SEL_CPLL) in rk3568_uart_get_rate()
2263 else in rk3568_uart_get_rate()
2267 } else if (src == CLK_UART_SEL_FRAC) { in rk3568_uart_get_rate()
2274 } else { in rk3568_uart_get_rate()
2290 } else if (priv->cpll_hz % rate == 0) { in rk3568_uart_set_rate()
2294 } else if (rate == OSC_HZ) { in rk3568_uart_set_rate()
2298 } else { in rk3568_uart_set_rate()
2369 else in rk3568_i2s3_get_rate()
2378 else in rk3568_i2s3_get_rate()
2387 else in rk3568_i2s3_get_rate()
2406 else if (p_src == CLK_I2S3_SRC_SEL_CPLL) in rk3568_i2s3_get_rate()
2408 else in rk3568_i2s3_get_rate()
2412 } else if (src == CLK_I2S3_SEL_FRAC) { in rk3568_i2s3_get_rate()
2419 } else { in rk3568_i2s3_get_rate()
2436 } else if (priv->cpll_hz % rate == 0) { in rk3568_i2s3_set_rate()
2440 } else if (rate == OSC_HZ / 2) { in rk3568_i2s3_set_rate()
2444 } else { in rk3568_i2s3_set_rate()
2461 } else { in rk3568_i2s3_set_rate()
2475 } else { in rk3568_i2s3_set_rate()
2489 else in rk3568_i2s3_set_rate()
2917 else if (clk->id == SCLK_SDMMC0_SAMPLE) in rk3568_mmc_get_phase()
2919 else if (clk->id == SCLK_SDMMC1_SAMPLE) in rk3568_mmc_get_phase()
2921 else in rk3568_mmc_get_phase()
2973 else if (clk->id == SCLK_SDMMC0_SAMPLE) in rk3568_mmc_set_phase()
2975 else if (clk->id == SCLK_SDMMC1_SAMPLE) in rk3568_mmc_set_phase()
2977 else in rk3568_mmc_set_phase()
3035 else in rk3568_gmac0_src_set_parent()
3052 else in rk3568_gmac1_src_set_parent()
3068 else if (parent->id == SCLK_GMAC0_RMII_SPEED) in rk3568_gmac0_tx_rx_set_parent()
3072 else in rk3568_gmac0_tx_rx_set_parent()
3089 else if (parent->id == SCLK_GMAC1_RMII_SPEED) in rk3568_gmac1_tx_rx_set_parent()
3093 else in rk3568_gmac1_tx_rx_set_parent()
3124 } else if (parent->id == PLL_HPLL) { in rk3568_dclk_vop_set_parent()
3127 } else if (parent->id == PLL_CPLL) { in rk3568_dclk_vop_set_parent()
3130 } else { in rk3568_dclk_vop_set_parent()
3162 } else { in rk3568_rkvdec_set_parent()
3182 } else { in rk3568_i2s3_set_parent()
3193 } else { in rk3568_i2s3_set_parent()
3305 else in rk3568_clk_probe()
3332 } else { in rk3568_clk_bind()
3345 } else { in rk3568_clk_bind()
3418 else in soc_clk_dump()
3429 else in soc_clk_dump()
3432 } else { in soc_clk_dump()
3436 else in soc_clk_dump()