clk/rockchip/clk_rk3562.c

47 	[APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
170 	old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,  in rk3562_armclk_set_rate()
171 					 APLL);  in rk3562_armclk_set_rate()
179 		if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],  in rk3562_armclk_set_rate()
180 					  priv->cru, APLL, new_rate))  in rk3562_armclk_set_rate()
194 		if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],  in rk3562_armclk_set_rate()
195 					  priv->cru, APLL, new_rate))  in rk3562_armclk_set_rate()
1367 		rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,  in rk3562_clk_get_rate()
1368 					     APLL);  in rk3562_clk_get_rate()
1795 			rockchip_pll_get_rate(&rk3562_pll_clks[APLL],  in rk3562_clk_init()
1796 					      priv->cru, APLL);  in rk3562_clk_init()