623 	int src_clk_div;  in rk3399_i2c_set_clk()  local
626 	src_clk_div = GPLL_HZ / hz;  in rk3399_i2c_set_clk()
627 	assert(src_clk_div - 1 <= 127);  in rk3399_i2c_set_clk()
632 			     I2C_CLK_REG_VALUE(1, src_clk_div));  in rk3399_i2c_set_clk()
636 			     I2C_CLK_REG_VALUE(2, src_clk_div));  in rk3399_i2c_set_clk()
640 			     I2C_CLK_REG_VALUE(3, src_clk_div));  in rk3399_i2c_set_clk()
644 			     I2C_CLK_REG_VALUE(5, src_clk_div));  in rk3399_i2c_set_clk()
648 			     I2C_CLK_REG_VALUE(6, src_clk_div));  in rk3399_i2c_set_clk()
652 			     I2C_CLK_REG_VALUE(7, src_clk_div));  in rk3399_i2c_set_clk()
723 	int src_clk_div;  in rk3399_spi_set_clk()  local
725 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;  in rk3399_spi_set_clk()
726 	assert(src_clk_div < 128);  in rk3399_spi_set_clk()
741 		     ((src_clk_div << spiclk->div_shift) |  in rk3399_spi_set_clk()
829 	int src_clk_div;  in rk3399_mmc_set_clk()  local
837 		src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);  in rk3399_mmc_set_clk()
839 		if (src_clk_div > 128) {  in rk3399_mmc_set_clk()
841 			src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);  in rk3399_mmc_set_clk()
842 			assert(src_clk_div - 1 < 128);  in rk3399_mmc_set_clk()
846 				     (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);  in rk3399_mmc_set_clk()
851 				     (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);  in rk3399_mmc_set_clk()
856 		src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);  in rk3399_mmc_set_clk()
857 		assert(src_clk_div - 1 < 32);  in rk3399_mmc_set_clk()
862 			     (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);  in rk3399_mmc_set_clk()
865 		src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);  in rk3399_mmc_set_clk()
866 		if (src_clk_div > 128) {  in rk3399_mmc_set_clk()
868 			src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate);  in rk3399_mmc_set_clk()
869 			assert(src_clk_div - 1 < 128);  in rk3399_mmc_set_clk()
873 				     (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);  in rk3399_mmc_set_clk()
878 				     (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);  in rk3399_mmc_set_clk()
971 	int src_clk_div;  in rk3399_saradc_set_clk()  local
973 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3399_saradc_set_clk()
974 	assert(src_clk_div <= 255);  in rk3399_saradc_set_clk()
978 		     src_clk_div << CLK_SARADC_DIV_CON_SHIFT);  in rk3399_saradc_set_clk()
996 	int src_clk_div;  in rk3399_tsadc_set_clk()  local
998 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3399_tsadc_set_clk()
999 	assert(src_clk_div <= 255);  in rk3399_tsadc_set_clk()
1004 		     (src_clk_div << CLK_TSADC_DIV_CON_SHIFT));  in rk3399_tsadc_set_clk()
1036 	int src_clk_div;  in rk3399_crypto_set_clk()  local
1038 	src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);  in rk3399_crypto_set_clk()
1039 	assert(src_clk_div - 1 <= 31);  in rk3399_crypto_set_clk()
1050 			     (src_clk_div - 1) << CRYPTO0_DIV_SHIFT);  in rk3399_crypto_set_clk()
1056 			     (src_clk_div - 1) << CRYPTO1_DIV_SHIFT);  in rk3399_crypto_set_clk()
1627 	int src_clk_div;  in rk3399_i2c_set_pmuclk()  local
1629 	src_clk_div = PPLL_HZ / hz;  in rk3399_i2c_set_pmuclk()
1630 	assert(src_clk_div - 1 < 127);  in rk3399_i2c_set_pmuclk()
1635 			     I2C_PMUCLK_REG_VALUE(0, src_clk_div));  in rk3399_i2c_set_pmuclk()
1639 			     I2C_PMUCLK_REG_VALUE(4, src_clk_div));  in rk3399_i2c_set_pmuclk()
1643 			     I2C_PMUCLK_REG_VALUE(8, src_clk_div));  in rk3399_i2c_set_pmuclk()
1650 	return DIV_TO_RATE(PPLL_HZ, src_clk_div);  in rk3399_i2c_set_pmuclk()