46 #define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))  argument
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)  in rkclk_set_pll()
445 static int pll_para_config(u32 freq_hz, struct pll_div *div)  in pll_para_config()
586 	u32 div, con;  in rk3399_i2c_get_clk()  local
701 	u32 div, val;  in rk3399_spi_get_clk()  local
754 	u32 div = 1;  in rk3399_vop_set_clk()  local
801 	u32 div, con;  in rk3399_mmc_get_clk()  local
960 	u32 div, val;  in rk3399_saradc_get_clk()  local
985 	u32 div, val;  in rk3399_tsadc_get_clk()  local
1012 	u32 div, con, parent;  in rk3399_crypto_get_clk()  local
1070 	u32 div, con, parent;  in rk3399_peri_get_clk()  local
1131 	u32 div, con, parent;  in rk3399_alive_get_clk()  local
1601 	u32 div, con;  in rk3399_i2c_get_pmuclk()  local
1655 	u32 div, con;  in rk3399_pwm_get_clk()  local