247 	ulong ret;  in rk3328_gmac2io_set_clk()  local
258 		ret = rate;  in rk3328_gmac2io_set_clk()
279 	return ret;  in rk3328_gmac2io_set_clk()
870 	ulong ret = 0;  in rk3328_clk_set_rate()  local
876 		ret = rockchip_pll_set_rate(&rk3328_pll_clks[clk->id - 1],  in rk3328_clk_set_rate()
880 		ret = rockchip_pll_set_rate(&rk3328_pll_clks[CPLL],  in rk3328_clk_set_rate()
885 		ret = rockchip_pll_set_rate(&rk3328_pll_clks[GPLL],  in rk3328_clk_set_rate()
891 			ret = rk3328_armclk_set_clk(priv, rate);  in rk3328_clk_set_rate()
908 		ret = rk3328_mmc_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
911 		ret = rk3328_spi_set_clk(priv, rate);  in rk3328_clk_set_rate()
918 		ret = rk3328_i2c_set_clk(priv, clk->id, rate);  in rk3328_clk_set_rate()
921 		ret = rk3328_gmac2io_set_clk(priv, rate);  in rk3328_clk_set_rate()
924 		ret = rk3328_gmac2phy_set_clk(priv->cru, rate);  in rk3328_clk_set_rate()
927 		ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate);  in rk3328_clk_set_rate()
930 		ret = rk3328_pwm_set_clk(priv, rate);  in rk3328_clk_set_rate()
933 		ret = rk3328_saradc_set_clk(priv, rate);  in rk3328_clk_set_rate()
936 		ret = rk3328_tsadc_set_clk(priv, rate);  in rk3328_clk_set_rate()
978 	return ret;  in rk3328_clk_set_rate()
986 	int ret;  in rk3328_gmac2io_set_parent()  local
1004 	ret = dev_read_string_index(parent->dev, "clock-output-names",  in rk3328_gmac2io_set_parent()
1006 	if (ret < 0)  in rk3328_gmac2io_set_parent()
1023 	int ret;  in rk3328_gmac2io_ext_set_parent()  local
1041 	ret = dev_read_string_index(parent->dev, "clock-output-names",  in rk3328_gmac2io_ext_set_parent()
1043 	if (ret < 0)  in rk3328_gmac2io_ext_set_parent()
1060 	int ret;  in rk3328_gmac2phy_set_parent()  local
1078 	ret = dev_read_string_index(parent->dev, "clock-output-names",  in rk3328_gmac2phy_set_parent()
1080 	if (ret < 0)  in rk3328_gmac2phy_set_parent()
1238 	int ret;  in rk3328_clk_get_phase()  local
1245 		ret = rk3328_mmc_get_phase(clk);  in rk3328_clk_get_phase()
1251 	return ret;  in rk3328_clk_get_phase()
1256 	int ret;  in rk3328_clk_set_phase()  local
1263 		ret = rk3328_mmc_set_phase(clk, degrees);  in rk3328_clk_set_phase()
1269 	return ret;  in rk3328_clk_set_phase()
1324 	int ret = 0;  in rk3328_clk_probe()  local
1337 	ret = clk_set_defaults(dev);  in rk3328_clk_probe()
1338 	if (ret)  in rk3328_clk_probe()
1339 		debug("%s clk_set_defaults failed %d\n", __func__, ret);  in rk3328_clk_probe()
1357 	int ret;  in rk3328_clk_bind()  local
1363 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",  in rk3328_clk_bind()
1365 	if (ret) {  in rk3328_clk_bind()
1366 		debug("Warning: No sysreset driver: ret=%d\n", ret);  in rk3328_clk_bind()
1376 	ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",  in rk3328_clk_bind()
1378 	if (ret) {  in rk3328_clk_bind()
1379 		debug("Warning: No rockchip reset driver: ret=%d\n", ret);  in rk3328_clk_bind()
1422 	int i, ret;  in soc_clk_dump()  local
1424 	ret = uclass_get_device_by_driver(UCLASS_CLK,  in soc_clk_dump()
1427 	if (ret) {  in soc_clk_dump()
1429 		return ret;  in soc_clk_dump()
1444 				ret = clk_request(cru_dev, &clk);  in soc_clk_dump()
1445 			if (ret < 0)  in soc_clk_dump()
1446 				return ret;  in soc_clk_dump()