230 	u32 src_clk_div, con_id;  in rk3308_i2c_set_clk()  local
232 	src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);  in rk3308_i2c_set_clk()
233 	assert(src_clk_div - 1 <= 127);  in rk3308_i2c_set_clk()
255 		     (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT);  in rk3308_i2c_set_clk()
340 	int src_clk_div;  in rk3308_mmc_set_clk()  local
359 	src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate);  in rk3308_mmc_set_clk()
361 	if (src_clk_div > 127) {  in rk3308_mmc_set_clk()
363 		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);  in rk3308_mmc_set_clk()
368 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);  in rk3308_mmc_set_clk()
374 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);  in rk3308_mmc_set_clk()
396 	int src_clk_div;  in rk3308_saradc_set_clk()  local
398 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in rk3308_saradc_set_clk()
399 	assert(src_clk_div - 1 <= 2047);  in rk3308_saradc_set_clk()
403 		     (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);  in rk3308_saradc_set_clk()
424 	int src_clk_div;  in rk3308_tsadc_set_clk()  local
426 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in rk3308_tsadc_set_clk()
427 	assert(src_clk_div - 1 <= 2047);  in rk3308_tsadc_set_clk()
431 		     (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);  in rk3308_tsadc_set_clk()
467 	u32 src_clk_div, con_id;  in rk3308_spi_set_clk()  local
469 	src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);  in rk3308_spi_set_clk()
470 	assert(src_clk_div - 1 <= 127);  in rk3308_spi_set_clk()
490 		     (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT);  in rk3308_spi_set_clk()
511 	int src_clk_div;  in rk3308_pwm_set_clk()  local
513 	src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);  in rk3308_pwm_set_clk()
514 	assert(src_clk_div - 1 <= 127);  in rk3308_pwm_set_clk()
519 		     (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);  in rk3308_pwm_set_clk()
645 	int src_clk_div;  in rk3308_bus_set_clk()  local
647 	src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);  in rk3308_bus_set_clk()
648 	assert(src_clk_div - 1 <= 31);  in rk3308_bus_set_clk()
659 			     (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT);  in rk3308_bus_set_clk()
664 			     (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT);  in rk3308_bus_set_clk()
669 			     (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT);  in rk3308_bus_set_clk()
708 	int src_clk_div;  in rk3308_peri_set_clk()  local
710 	src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);  in rk3308_peri_set_clk()
711 	assert(src_clk_div - 1 <= 31);  in rk3308_peri_set_clk()
722 			     (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);  in rk3308_peri_set_clk()
727 			     (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT);  in rk3308_peri_set_clk()
732 			     (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT);  in rk3308_peri_set_clk()
767 	int src_clk_div;  in rk3308_audio_set_clk()  local
769 	src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);  in rk3308_audio_set_clk()
770 	assert(src_clk_div - 1 <= 31);  in rk3308_audio_set_clk()
781 			     (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT);  in rk3308_audio_set_clk()
787 			     (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT);  in rk3308_audio_set_clk()
824 	int src_clk_div;  in rk3308_crypto_set_clk()  local
826 	src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);  in rk3308_crypto_set_clk()
827 	assert(src_clk_div - 1 <= 31);  in rk3308_crypto_set_clk()
838 			     (src_clk_div - 1) << CRYPTO_DIV_SHIFT);  in rk3308_crypto_set_clk()
844 			     (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT);  in rk3308_crypto_set_clk()
916 	int src_clk_div;  in rk3308_sclk_sfc_set_clk()  local
918 	src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);  in rk3308_sclk_sfc_set_clk()
919 	assert(src_clk_div - 1 <= 127);  in rk3308_sclk_sfc_set_clk()
924 		     (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT);  in rk3308_sclk_sfc_set_clk()