210 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
236 			 const struct pll_div *div)  in rkclk_set_pll()
355 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()
450 		u8 div;  in rockchip_mac_set_clk()  local
718 	uint div, mux;  in rockchip_mmc_get_clk()  local
802 	uint div, mux;  in rockchip_spi_get_clk()  local
865 	uint div, mux;  in rockchip_aclk_peri_get_clk()  local
883 	uint div, mux;  in rockchip_aclk_cpu_get_clk()  local
904 	uint div;  in rockchip_pclk_peri_get_clk()  local
918 	uint div;  in rockchip_pclk_cpu_get_clk()  local
948 	u32 div, val;  in rockchip_saradc_get_clk()  local
973 	u32 div, val;  in rockchip_tsadc_get_clk()  local
1000 	u32 div, val;  in rockchip_crypto_get_clk()  local
1026 	u32 div, con, parent;  in rk3288_alive_get_clk()  local