181 	int src_clk_div;  in rockchip_mmc_set_clk()  local
185 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq);  in rockchip_mmc_set_clk()
187 	if (src_clk_div > 128) {  in rockchip_mmc_set_clk()
188 		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);  in rockchip_mmc_set_clk()
200 			     (src_clk_div - 1) << EMMC_DIV_SHIFT);  in rockchip_mmc_set_clk()
207 			     (src_clk_div - 1) << MMC0_DIV_SHIFT);  in rockchip_mmc_set_clk()
214 			     (src_clk_div - 1) << SDIO_DIV_SHIFT);  in rockchip_mmc_set_clk()
262 	int src_clk_div;  in rk3128_peri_set_clk()  local
266 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3128_peri_set_clk()
267 		assert(src_clk_div - 1 < 32);  in rk3128_peri_set_clk()
271 			     (src_clk_div - 1) << ACLK_PERI_DIV_SHIFT);  in rk3128_peri_set_clk()
279 		src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv,  in rk3128_peri_set_clk()
282 		assert(src_clk_div - 1 < 3);  in rk3128_peri_set_clk()
285 			     (src_clk_div - 1) << PCLK_PERI_DIV_SHIFT);  in rk3128_peri_set_clk()
288 		src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv,  in rk3128_peri_set_clk()
291 		assert(src_clk_div - 1 < 7);  in rk3128_peri_set_clk()
294 			     (src_clk_div - 1) << HCLK_PERI_DIV_SHIFT);  in rk3128_peri_set_clk()
337 	int src_clk_div;  in rk3128_bus_set_clk()  local
341 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk3128_bus_set_clk()
342 		assert(src_clk_div - 1 < 32);  in rk3128_bus_set_clk()
346 			     (src_clk_div - 1) << ACLK_BUS_DIV_SHIFT);  in rk3128_bus_set_clk()
349 		src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv,  in rk3128_bus_set_clk()
352 		assert(src_clk_div - 1 < 3);  in rk3128_bus_set_clk()
355 			     (src_clk_div - 1) << PCLK_BUS_DIV_SHIFT);  in rk3128_bus_set_clk()
358 		src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv,  in rk3128_bus_set_clk()
361 		assert(src_clk_div - 1 < 7);  in rk3128_bus_set_clk()
364 			     (src_clk_div - 1) << HCLK_BUS_DIV_SHIFT);  in rk3128_bus_set_clk()
416 	int src_clk_div;  in rk3128_saradc_set_clk()  local
418 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;  in rk3128_saradc_set_clk()
419 	assert(src_clk_div < 128);  in rk3128_saradc_set_clk()
423 		     src_clk_div << SARADC_DIV_CON_SHIFT);  in rk3128_saradc_set_clk()
434 	int src_clk_div;  in rk3128_vop_set_clk()  local
436 	src_clk_div = GPLL_HZ / hz;  in rk3128_vop_set_clk()
437 	assert(src_clk_div - 1 < 31);  in rk3128_vop_set_clk()
445 			     (src_clk_div - 1) << VIO0_DIV_SHIFT);  in rk3128_vop_set_clk()
451 			     (src_clk_div - 1) << VIO1_DIV_SHIFT);  in rk3128_vop_set_clk()
454 		src_clk_div = DIV_ROUND_UP(RK3128_LCDC_PLL_LIMIT, hz);  in rk3128_vop_set_clk()
456 				      priv->cru, CPLL, src_clk_div * hz);  in rk3128_vop_set_clk()
460 			     (src_clk_div - 1) << DCLK_VOP_DIV_CON_SHIFT);  in rk3128_vop_set_clk()
514 	int src_clk_div;  in rk3128_crypto_set_rate()  local
518 	src_clk_div = DIV_ROUND_UP(p_rate, hz) - 1;  in rk3128_crypto_set_rate()
519 	assert(src_clk_div < 3);  in rk3128_crypto_set_rate()
523 		     src_clk_div << CLK_CRYPTO_DIV_CON_SHIFT);  in rk3128_crypto_set_rate()