76 	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&  in rkclk_set_pll()
125 	assert((aclk_div + 1) * CORE_ACLK_HZ <= APLL_HZ && aclk_div < 0x7);  in rkclk_init()
128 	assert((pclk_div + 1) * CORE_PERI_HZ <= APLL_HZ && pclk_div < 0xf);  in rkclk_init()
145 	assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f);  in rkclk_init()
148 	assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7);  in rkclk_init()
151 	assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3);  in rkclk_init()
168 	assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f);  in rkclk_init()
171 	assert((1 << hclk_div) * PERI_HCLK_HZ <=  in rkclk_init()
175 	assert((1 << pclk_div) * PERI_PCLK_HZ <=  in rkclk_init()
291 		assert(src_clk_div - 1 < 128);  in rockchip_mmc_set_clk()
353 	assert(div - 1 < 128);  in rk3036_spi_set_clk()
383 	assert(src_clk_div - 1 <= 255);  in rockchip_dclk_lcdc_set_clk()
415 	assert(src_clk_div - 1 <= 31);  in rockchip_aclk_lcdc_set_clk()
460 		assert(src_clk_div - 1 < 32);  in rk3036_peri_set_clk()
471 		assert(src_clk_div - 1 < 8);  in rk3036_peri_set_clk()