Lines Matching refs:src_clk_div
137 int src_clk_div; in rk1808_i2c_set_clk() local
139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
140 assert(src_clk_div - 1 < 127); in rk1808_i2c_set_clk()
146 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
152 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
158 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
164 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
170 (src_clk_div - 1) << CLK_I2C4_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
176 (src_clk_div - 1) << CLK_I2C5_DIV_CON_SHIFT | in rk1808_i2c_set_clk()
225 int src_clk_div; in rk1808_mmc_set_clk() local
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
249 if (src_clk_div > 127) { in rk1808_mmc_set_clk()
251 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk1808_mmc_set_clk()
255 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
260 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rk1808_mmc_set_clk()
283 int src_clk_div; in rk1808_sfc_set_clk() local
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
289 (src_clk_div - 1) << SFC_DIV_CON_SHIFT); in rk1808_sfc_set_clk()
308 int src_clk_div; in rk1808_saradc_set_clk() local
310 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_saradc_set_clk()
311 assert(src_clk_div - 1 < 2047); in rk1808_saradc_set_clk()
315 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_saradc_set_clk()
351 int src_clk_div; in rk1808_pwm_set_clk() local
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
354 assert(src_clk_div - 1 < 127); in rk1808_pwm_set_clk()
360 (src_clk_div - 1) << CLK_PWM0_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
366 (src_clk_div - 1) << CLK_PWM1_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
372 (src_clk_div - 1) << CLK_PWM2_DIV_CON_SHIFT | in rk1808_pwm_set_clk()
397 int src_clk_div; in rk1808_tsadc_set_clk() local
399 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_tsadc_set_clk()
400 assert(src_clk_div - 1 < 2047); in rk1808_tsadc_set_clk()
404 (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT); in rk1808_tsadc_set_clk()
439 int src_clk_div; in rk1808_spi_set_clk() local
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
442 assert(src_clk_div - 1 < 127); in rk1808_spi_set_clk()
448 (src_clk_div - 1) << CLK_SPI0_DIV_CON_SHIFT | in rk1808_spi_set_clk()
454 (src_clk_div - 1) << CLK_SPI1_DIV_CON_SHIFT | in rk1808_spi_set_clk()
460 (src_clk_div - 1) << CLK_SPI2_DIV_CON_SHIFT | in rk1808_spi_set_clk()
520 int src_clk_div, parent; in rk1808_vop_set_clk() local
522 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
523 assert(src_clk_div - 1 < 31); in rk1808_vop_set_clk()
531 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
535 src_clk_div = in rk1808_vop_set_clk()
537 assert(src_clk_div - 1 < 15); in rk1808_vop_set_clk()
540 (src_clk_div - 1) << HCLK_VOP_DIV_CON_SHIFT); in rk1808_vop_set_clk()
546 src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ, hz); in rk1808_vop_set_clk()
555 ((src_clk_div - 1) << DCLK_VOPRAW_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
557 priv->cru, NPLL, src_clk_div * hz); in rk1808_vop_set_clk()
566 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk1808_vop_set_clk()
569 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
572 src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ, in rk1808_vop_set_clk()
576 src_clk_div * hz); in rk1808_vop_set_clk()
584 ((src_clk_div - 1) << DCLK_VOPLITE_DIV_CON_SHIFT)); in rk1808_vop_set_clk()
682 int src_clk_div; in rk1808_crypto_set_clk() local
684 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_crypto_set_clk()
685 assert(src_clk_div - 1 <= 31); in rk1808_crypto_set_clk()
696 (src_clk_div - 1) << CRYPTO_DIV_SHIFT); in rk1808_crypto_set_clk()
702 (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT); in rk1808_crypto_set_clk()
746 int src_clk_div; in rk1808_bus_set_clk() local
754 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
755 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
759 (src_clk_div - 1) << HSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
762 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
763 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
767 (src_clk_div - 1) << MSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
770 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_bus_set_clk()
771 assert(src_clk_div - 1 < 31); in rk1808_bus_set_clk()
775 (src_clk_div - 1) << LSCLK_BUS_DIV_CON_SHIFT); in rk1808_bus_set_clk()
814 int src_clk_div; in rk1808_peri_set_clk() local
816 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_peri_set_clk()
817 assert(src_clk_div - 1 < 31); in rk1808_peri_set_clk()
828 (src_clk_div - 1) << MSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
834 (src_clk_div - 1) << LSCLK_PERI_DIV_CON_SHIFT); in rk1808_peri_set_clk()
848 int src_clk_div; in rk1808_pclk_pmu_set_clk() local
850 src_clk_div = DIV_ROUND_UP(parent_hz, hz); in rk1808_pclk_pmu_set_clk()
851 assert(src_clk_div - 1 < 31); in rk1808_pclk_pmu_set_clk()
855 (src_clk_div - 1) << PCLK_PMU_DIV_CON_SHIFT); in rk1808_pclk_pmu_set_clk()
857 return parent_hz / src_clk_div; in rk1808_pclk_pmu_set_clk()