315 			     pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
357 		rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3036_pll_set_rate()
380 	mask = pll->mode_mask << shift;  in rk3036_pll_get_rate()
467 		     pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
471 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
475 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
479 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
509 	rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,  in rk3588_pll_set_rate()
513 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
523 			     pll->mode_mask << 6,  in rk3588_pll_set_rate()
533 			     pll->mode_mask << 14,  in rk3588_pll_set_rate()
573 		mode = (con & (pll->mode_mask << shift)) >> shift;  in rk3588_pll_get_rate()
628 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
632 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_get_rate()
636 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_get_rate()
657 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()
661 		pll->mode_mask = PLL_RK3328_MODE_MASK;  in rockchip_pll_set_rate()
665 		pll->mode_mask = PLL_MODE_MASK;  in rockchip_pll_set_rate()