82 static int rockchip_pll_clk_set_postdiv(ulong fout_hz,  in rockchip_pll_clk_set_postdiv()  argument
89 	if (fout_hz < MIN_FOUTVCO_FREQ) {  in rockchip_pll_clk_set_postdiv()
92 				freq = fout_hz * (*postdiv1) * (*postdiv2);  in rockchip_pll_clk_set_postdiv()
101 		       fout_hz);  in rockchip_pll_clk_set_postdiv()
111 			     ulong fout_hz)  in rockchip_pll_clk_set_by_auto()  argument
115 	u32 foutvco = fout_hz;  in rockchip_pll_clk_set_by_auto()
120 	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)  in rockchip_pll_clk_set_by_auto()
123 	rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);  in rockchip_pll_clk_set_by_auto()
128 	if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {  in rockchip_pll_clk_set_by_auto()
138 		      fin_hz, fout_hz, clk_gcd);  in rockchip_pll_clk_set_by_auto()
145 		      fin_hz, fout_hz);  in rockchip_pll_clk_set_by_auto()
193 rockchip_rk3588_pll_frac_by_auto(unsigned long fin_hz, unsigned long fout_hz)  in rockchip_rk3588_pll_frac_by_auto()  argument
200 		fvco = (u64)fout_hz << s;  in rockchip_rk3588_pll_frac_by_auto()
229 			   unsigned long fout_hz)  in rk3588_pll_clk_set_by_auto()  argument
235 	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)  in rk3588_pll_clk_set_by_auto()
238 	if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ)  in rk3588_pll_clk_set_by_auto()
241 	if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {  in rk3588_pll_clk_set_by_auto()
243 			fvco = fout_hz << s;  in rk3588_pll_clk_set_by_auto()
259 		pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);  in rk3588_pll_clk_set_by_auto()
261 		rate_table = rockchip_rk3588_pll_frac_by_auto(fin_hz, fout_hz);  in rk3588_pll_clk_set_by_auto()
264 			       fout_hz);  in rk3588_pll_clk_set_by_auto()