drivers/clk/clk_zynqmp.c

18 static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;  variable
22 #define CRF_APB_APLL_CTRL		(zynqmp_crf_apb_clkc_base + 0x00)
23 #define CRF_APB_DPLL_CTRL		(zynqmp_crf_apb_clkc_base + 0x0c)
24 #define CRF_APB_VPLL_CTRL		(zynqmp_crf_apb_clkc_base + 0x18)
25 #define CRF_APB_PLL_STATUS		(zynqmp_crf_apb_clkc_base + 0x24)
26 #define CRF_APB_APLL_TO_LPD_CTRL	(zynqmp_crf_apb_clkc_base + 0x28)
27 #define CRF_APB_DPLL_TO_LPD_CTRL	(zynqmp_crf_apb_clkc_base + 0x2c)
28 #define CRF_APB_VPLL_TO_LPD_CTRL	(zynqmp_crf_apb_clkc_base + 0x30)
30 #define CRF_APB_ACPU_CTRL		(zynqmp_crf_apb_clkc_base + 0x40)
31 #define CRF_APB_DBG_TRACE_CTRL		(zynqmp_crf_apb_clkc_base + 0x44)
32 #define CRF_APB_DBG_FPD_CTRL		(zynqmp_crf_apb_clkc_base + 0x48)
33 #define CRF_APB_DP_VIDEO_REF_CTRL	(zynqmp_crf_apb_clkc_base + 0x50)
34 #define CRF_APB_DP_AUDIO_REF_CTRL	(zynqmp_crf_apb_clkc_base + 0x54)
35 #define CRF_APB_DP_STC_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x5c)
36 #define CRF_APB_DDR_CTRL		(zynqmp_crf_apb_clkc_base + 0x60)
37 #define CRF_APB_GPU_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x64)
38 #define CRF_APB_SATA_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x80)
39 #define CRF_APB_PCIE_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x94)
40 #define CRF_APB_GDMA_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x98)
41 #define CRF_APB_DPDMA_REF_CTRL		(zynqmp_crf_apb_clkc_base + 0x9c)
42 #define CRF_APB_TOPSW_MAIN_CTRL		(zynqmp_crf_apb_clkc_base + 0xa0)
43 #define CRF_APB_TOPSW_LSBUS_CTRL	(zynqmp_crf_apb_clkc_base + 0xa4)
44 #define CRF_APB_GTGREF0_REF_CTRL	(zynqmp_crf_apb_clkc_base + 0xa8)
45 #define CRF_APB_DBG_TSTMP_CTRL		(zynqmp_crf_apb_clkc_base + 0xd8)