Lines Matching refs:value
99 u32 value; in tegra_xusb_padctl_enable() local
104 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
105 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra_xusb_padctl_enable()
106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
111 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra_xusb_padctl_enable()
112 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
116 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
117 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra_xusb_padctl_enable()
118 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_enable()
125 u32 value; in tegra_xusb_padctl_disable() local
135 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
136 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra_xusb_padctl_disable()
137 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
141 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
142 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra_xusb_padctl_disable()
143 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
147 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
148 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra_xusb_padctl_disable()
149 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra_xusb_padctl_disable()
220 u32 value; in pcie_phy_enable() local
224 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
225 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK; in pcie_phy_enable()
226 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136); in pcie_phy_enable()
227 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
229 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
230 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; in pcie_phy_enable()
231 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a); in pcie_phy_enable()
232 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
234 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
235 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
238 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
239 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; in pcie_phy_enable()
240 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
242 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
243 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; in pcie_phy_enable()
244 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
247 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; in pcie_phy_enable()
248 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK; in pcie_phy_enable()
249 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); in pcie_phy_enable()
250 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN; in pcie_phy_enable()
251 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
253 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
254 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; in pcie_phy_enable()
255 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; in pcie_phy_enable()
256 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25); in pcie_phy_enable()
257 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
259 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
260 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ; in pcie_phy_enable()
261 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
263 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
264 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK; in pcie_phy_enable()
265 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
269 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
270 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN; in pcie_phy_enable()
271 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in pcie_phy_enable()
273 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
274 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; in pcie_phy_enable()
275 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
282 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
283 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) in pcie_phy_enable()
286 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) { in pcie_phy_enable()
292 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
293 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN; in pcie_phy_enable()
294 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
301 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
302 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0) in pcie_phy_enable()
305 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) { in pcie_phy_enable()
311 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
312 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; in pcie_phy_enable()
313 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
319 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
320 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS) in pcie_phy_enable()
323 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) { in pcie_phy_enable()
329 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
330 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; in pcie_phy_enable()
331 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; in pcie_phy_enable()
332 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
338 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
339 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) in pcie_phy_enable()
342 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) { in pcie_phy_enable()
348 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
349 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN; in pcie_phy_enable()
350 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
356 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
357 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0) in pcie_phy_enable()
360 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) { in pcie_phy_enable()
366 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
367 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN; in pcie_phy_enable()
368 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
370 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
371 value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in pcie_phy_enable()
372 value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; in pcie_phy_enable()
373 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; in pcie_phy_enable()
374 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; in pcie_phy_enable()
375 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
378 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()
379 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in pcie_phy_enable()
381 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
382 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD; in pcie_phy_enable()
383 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in pcie_phy_enable()
385 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
386 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD; in pcie_phy_enable()
387 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in pcie_phy_enable()
391 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()
392 value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE; in pcie_phy_enable()
393 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()