Lines Matching defs:emif_reg_struct
608 struct emif_reg_struct { struct
609 u32 emif_mod_id_rev;
610 u32 emif_status;
611 u32 emif_sdram_config;
612 u32 emif_lpddr2_nvm_config;
613 u32 emif_sdram_ref_ctrl;
614 u32 emif_sdram_ref_ctrl_shdw;
615 u32 emif_sdram_tim_1;
616 u32 emif_sdram_tim_1_shdw;
617 u32 emif_sdram_tim_2;
618 u32 emif_sdram_tim_2_shdw;
619 u32 emif_sdram_tim_3;
620 u32 emif_sdram_tim_3_shdw;
621 u32 emif_lpddr2_nvm_tim;
622 u32 emif_lpddr2_nvm_tim_shdw;
623 u32 emif_pwr_mgmt_ctrl;
624 u32 emif_pwr_mgmt_ctrl_shdw;
625 u32 emif_lpddr2_mode_reg_data;
626 u32 padding1[1];
627 u32 emif_lpddr2_mode_reg_data_es2;
628 u32 padding11[1];
629 u32 emif_lpddr2_mode_reg_cfg;
630 u32 emif_l3_config;
631 u32 emif_l3_cfg_val_1;
632 u32 emif_l3_cfg_val_2;
633 u32 emif_iodft_tlgc;
634 u32 padding2[7];
635 u32 emif_perf_cnt_1;
636 u32 emif_perf_cnt_2;
637 u32 emif_perf_cnt_cfg;
638 u32 emif_perf_cnt_sel;
639 u32 emif_perf_cnt_tim;
640 u32 padding3;
641 u32 emif_read_idlectrl;
642 u32 emif_read_idlectrl_shdw;
643 u32 padding4;
644 u32 emif_irqstatus_raw_sys;
645 u32 emif_irqstatus_raw_ll;
646 u32 emif_irqstatus_sys;
647 u32 emif_irqstatus_ll;
648 u32 emif_irqenable_set_sys;
649 u32 emif_irqenable_set_ll;
650 u32 emif_irqenable_clr_sys;
651 u32 emif_irqenable_clr_ll;
652 u32 padding5;
653 u32 emif_zq_config;
654 u32 emif_temp_alert_config;
655 u32 emif_l3_err_log;
656 u32 emif_rd_wr_lvl_rmp_win;
657 u32 emif_rd_wr_lvl_rmp_ctl;
658 u32 emif_rd_wr_lvl_ctl;
659 u32 padding6[1];
660 u32 emif_ddr_phy_ctrl_1;
661 u32 emif_ddr_phy_ctrl_1_shdw;
662 u32 emif_ddr_phy_ctrl_2;
663 u32 padding7[4];
664 u32 emif_prio_class_serv_map;
665 u32 emif_connect_id_serv_1_map;
666 u32 emif_connect_id_serv_2_map;
667 u32 padding8[5];
668 u32 emif_rd_wr_exec_thresh;
669 u32 emif_cos_config;
670 u32 padding9[6];
671 u32 emif_ddr_phy_status[28];
672 u32 padding10[20];
673 u32 emif_ddr_ext_phy_ctrl_1;
674 u32 emif_ddr_ext_phy_ctrl_1_shdw;
675 u32 emif_ddr_ext_phy_ctrl_2;
676 u32 emif_ddr_ext_phy_ctrl_2_shdw;
677 u32 emif_ddr_ext_phy_ctrl_3;
678 u32 emif_ddr_ext_phy_ctrl_3_shdw;
679 u32 emif_ddr_ext_phy_ctrl_4;
680 u32 emif_ddr_ext_phy_ctrl_4_shdw;
681 u32 emif_ddr_ext_phy_ctrl_5;
682 u32 emif_ddr_ext_phy_ctrl_5_shdw;
683 u32 emif_ddr_ext_phy_ctrl_6;
684 u32 emif_ddr_ext_phy_ctrl_6_shdw;
685 u32 emif_ddr_ext_phy_ctrl_7;
686 u32 emif_ddr_ext_phy_ctrl_7_shdw;
687 u32 emif_ddr_ext_phy_ctrl_8;
688 u32 emif_ddr_ext_phy_ctrl_8_shdw;
689 u32 emif_ddr_ext_phy_ctrl_9;
690 u32 emif_ddr_ext_phy_ctrl_9_shdw;
691 u32 emif_ddr_ext_phy_ctrl_10;
692 u32 emif_ddr_ext_phy_ctrl_10_shdw;
693 u32 emif_ddr_ext_phy_ctrl_11;
694 u32 emif_ddr_ext_phy_ctrl_11_shdw;
695 u32 emif_ddr_ext_phy_ctrl_12;
696 u32 emif_ddr_ext_phy_ctrl_12_shdw;
697 u32 emif_ddr_ext_phy_ctrl_13;
698 u32 emif_ddr_ext_phy_ctrl_13_shdw;
699 u32 emif_ddr_ext_phy_ctrl_14;
700 u32 emif_ddr_ext_phy_ctrl_14_shdw;
701 u32 emif_ddr_ext_phy_ctrl_15;
702 u32 emif_ddr_ext_phy_ctrl_15_shdw;
703 u32 emif_ddr_ext_phy_ctrl_16;
704 u32 emif_ddr_ext_phy_ctrl_16_shdw;
705 u32 emif_ddr_ext_phy_ctrl_17;
706 u32 emif_ddr_ext_phy_ctrl_17_shdw;
707 u32 emif_ddr_ext_phy_ctrl_18;
708 u32 emif_ddr_ext_phy_ctrl_18_shdw;
709 u32 emif_ddr_ext_phy_ctrl_19;
710 u32 emif_ddr_ext_phy_ctrl_19_shdw;
711 u32 emif_ddr_ext_phy_ctrl_20;
712 u32 emif_ddr_ext_phy_ctrl_20_shdw;
713 u32 emif_ddr_ext_phy_ctrl_21;
714 u32 emif_ddr_ext_phy_ctrl_21_shdw;
715 u32 emif_ddr_ext_phy_ctrl_22;
716 u32 emif_ddr_ext_phy_ctrl_22_shdw;
717 u32 emif_ddr_ext_phy_ctrl_23;
718 u32 emif_ddr_ext_phy_ctrl_23_shdw;
719 u32 emif_ddr_ext_phy_ctrl_24;
720 u32 emif_ddr_ext_phy_ctrl_24_shdw;
721 u32 emif_ddr_ext_phy_ctrl_25;
722 u32 emif_ddr_ext_phy_ctrl_25_shdw;
723 u32 emif_ddr_ext_phy_ctrl_26;
724 u32 emif_ddr_ext_phy_ctrl_26_shdw;
725 u32 emif_ddr_ext_phy_ctrl_27;
726 u32 emif_ddr_ext_phy_ctrl_27_shdw;
727 u32 emif_ddr_ext_phy_ctrl_28;
728 u32 emif_ddr_ext_phy_ctrl_28_shdw;
729 u32 emif_ddr_ext_phy_ctrl_29;
730 u32 emif_ddr_ext_phy_ctrl_29_shdw;
731 u32 emif_ddr_ext_phy_ctrl_30;
732 u32 emif_ddr_ext_phy_ctrl_30_shdw;
733 u32 emif_ddr_ext_phy_ctrl_31;
734 u32 emif_ddr_ext_phy_ctrl_31_shdw;
735 u32 emif_ddr_ext_phy_ctrl_32;
736 u32 emif_ddr_ext_phy_ctrl_32_shdw;
737 u32 emif_ddr_ext_phy_ctrl_33;
738 u32 emif_ddr_ext_phy_ctrl_33_shdw;
739 u32 emif_ddr_ext_phy_ctrl_34;
740 u32 emif_ddr_ext_phy_ctrl_34_shdw;
741 u32 emif_ddr_ext_phy_ctrl_35;
742 u32 emif_ddr_ext_phy_ctrl_35_shdw;
743 union {
747 union {