412 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)  argument
415 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                       (((v) & 0x7) << 18)  argument
418 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)  argument
422 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)  argument
425 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)  argument
429 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)		(((v) & 0x7) << 15)  argument
432 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)		(((v) & 0x3) << 16)  argument
442 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			\  argument
444 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :		\
445 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
986 #define BF_ANADIG_PLL_SYS_RSVD0(v)  \  argument
987 	(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
994 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \  argument
995 	(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
1009 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \  argument
1010 	(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
1015 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \  argument
1016 	(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
1020 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \  argument
1021 	(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
1037 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \  argument
1038 	(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
1041 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \  argument
1042 	(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
1047 #define BF_ANADIG_PLL_528_RSVD1(v)  \  argument
1048 	(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
1054 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \  argument
1055 	(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1069 #define BF_ANADIG_PLL_528_RSVD0(v)  \  argument
1070 	(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
1075 #define BF_ANADIG_PLL_528_SS_STOP(v) \  argument
1076 	(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
1080 #define BF_ANADIG_PLL_528_SS_STEP(v)  \  argument
1081 	(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
1085 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \  argument
1086 	(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
1089 #define BF_ANADIG_PLL_528_NUM_A(v)  \  argument
1090 	(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
1094 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \  argument
1095 	(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
1098 #define BF_ANADIG_PLL_528_DENOM_B(v)  \  argument
1099 	(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
1104 #define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \  argument
1105 	(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
1109 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \  argument
1110 	(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1116 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \  argument
1117 	(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1131 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \  argument
1132 	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1136 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \  argument
1137 	(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
1140 #define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \  argument
1141 	(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
1145 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \  argument
1146 	(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
1149 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \  argument
1150 	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
1155 #define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \  argument
1156 	(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
1160 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)  \  argument
1161 	(((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1167 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \  argument
1168 	(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1182 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \  argument
1183 	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1187 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \  argument
1188 	(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
1191 #define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \  argument
1192 	(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
1196 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \  argument
1197 	(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
1200 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \  argument
1201 	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
1206 #define BF_ANADIG_PLL_ENET_RSVD1(v)  \  argument
1207 	(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
1216 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \  argument
1217 	(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1231 #define BF_ANADIG_PLL_ENET_RSVD0(v)  \  argument
1232 	(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1235 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \  argument
1236 	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1241 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \  argument
1242 	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
1248 #define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \  argument
1249 	(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1254 #define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \  argument
1255 	(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1260 #define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \  argument
1261 	(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1266 #define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \  argument
1267 	(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1273 #define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \  argument
1274 	(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1279 #define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \  argument
1280 	(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1285 #define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \  argument
1286 	(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1291 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \  argument
1292 	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1304 #define PMU_MISC2_AUDIO_DIV(v) \  argument
1305 	(((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
1307 	((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \