Lines Matching defs:ccsr_gur
90 struct ccsr_gur { struct
91 u32 porsr1; /* POR status 1 */
92 u32 porsr2; /* POR status 2 */
93 u8 res_008[0x20-0x8];
94 u32 gpporcr1; /* General-purpose POR configuration */
95 u32 gpporcr2;
96 u32 dcfg_fusesr; /* Fuse status register */
97 u8 res_02c[0x70-0x2c];
98 u32 devdisr; /* Device disable control */
99 u32 devdisr2; /* Device disable control 2 */
100 u32 devdisr3; /* Device disable control 3 */
101 u32 devdisr4; /* Device disable control 4 */
102 u32 devdisr5; /* Device disable control 5 */
103 u8 res_084[0x94-0x84];
104 u32 coredisru; /* uppper portion for support of 64 cores */
105 u32 coredisrl; /* lower portion for support of 64 cores */
106 u8 res_09c[0xa4-0x9c];
107 u32 svr; /* System version */
108 u8 res_0a8[0xb0-0xa8];
109 u32 rstcr; /* Reset control */
110 u32 rstrqpblsr; /* Reset request preboot loader status */
111 u8 res_0b8[0xc0-0xb8];
112 u32 rstrqmr1; /* Reset request mask */
113 u8 res_0c4[0xc8-0xc4];
114 u32 rstrqsr1; /* Reset request status */
115 u8 res_0cc[0xd4-0xcc];
116 u32 rstrqwdtmrl; /* Reset request WDT mask */
117 u8 res_0d8[0xdc-0xd8];
118 u32 rstrqwdtsrl; /* Reset request WDT status */
119 u8 res_0e0[0xe4-0xe0];
120 u32 brrl; /* Boot release */
121 u8 res_0e8[0x100-0xe8];
122 u32 rcwsr[16]; /* Reset control word status */
125 u8 res_140[0x200-0x140];
126 u32 scratchrw[4]; /* Scratch Read/Write */
127 u8 res_210[0x300-0x210];
128 u32 scratchw1r[4]; /* Scratch Read (Write once) */
129 u8 res_310[0x400-0x310];
130 u32 crstsr;
131 u8 res_404[0x550-0x404];
132 u32 sataliodnr;
133 u8 res_554[0x604-0x554];
134 u32 pamubypenr;
135 u32 dmacr1;
136 u8 res_60c[0x740-0x60c]; /* add more registers when needed */
137 u32 tp_ityp[64]; /* Topology Initiator Type Register */
138 struct {
141 } tp_cluster[1]; /* Core Cluster n Topology Register */
142 u8 res_848[0xe60-0x848];
143 u32 ddrclkdr;
144 u8 res_e60[0xe68-0xe64];
145 u32 ifcclkdr;
146 u8 res_e68[0xe80-0xe6c];
147 u32 sdhcpcr;