Lines Matching refs:__REG
15 # define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) macro
16 # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
18 # define __REG(x) (x) macro
60 #define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
61 #define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
62 #define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
65 #define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
66 #define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
67 #define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
70 #define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
71 #define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
72 #define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
73 #define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
74 #define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
75 #define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
76 #define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
77 #define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
78 #define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
79 #define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
80 #define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
81 #define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
82 #define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
86 #define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
87 #define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
88 #define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
89 #define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
92 #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
101 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
102 #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
103 #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
104 #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
105 #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
310 #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
311 #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
312 #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
313 #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
334 #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
335 #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
336 #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
337 #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
338 #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
339 #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
340 #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
341 #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
342 #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
343 #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
344 #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
345 #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
346 #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
347 #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
392 #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
394 #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
398 #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
401 #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
408 #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
414 #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
419 #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
447 #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
452 #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
457 #define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
460 #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
467 #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
475 #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
480 #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
484 #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
488 #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
612 #define TCTL1 __REG(IMX_TIM1_BASE)
613 #define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
614 #define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
615 #define TCR1 __REG(IMX_TIM1_BASE + 0xc)
616 #define TCN1 __REG(IMX_TIM1_BASE + 0x10)
617 #define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
618 #define TCTL2 __REG(IMX_TIM2_BASE)
619 #define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
620 #define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
621 #define TCR2 __REG(IMX_TIM2_BASE + 0xc)
622 #define TCN2 __REG(IMX_TIM2_BASE + 0x10)
623 #define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)