Lines Matching defs:ccsr_gur
176 struct ccsr_gur { struct
177 u32 porsr1; /* POR status 1 */
179 u32 porsr2; /* POR status 2 */
180 u8 res_008[0x20-0x8];
181 u32 gpporcr1; /* General-purpose POR configuration */
182 u32 gpporcr2;
187 u32 dcfg_fusesr; /* Fuse status register */
188 u8 res_02c[0x70-0x2c];
189 u32 devdisr; /* Device disable control */
202 u32 devdisr2; /* Device disable control 2 */
203 u32 devdisr3; /* Device disable control 3 */
204 u32 devdisr4; /* Device disable control 4 */
205 u32 devdisr5; /* Device disable control 5 */
206 u32 devdisr6; /* Device disable control 6 */
207 u32 devdisr7; /* Device disable control 7 */
208 u8 res_08c[0x94-0x8c];
209 u32 coredisru; /* uppper portion for support of 64 cores */
210 u32 coredisrl; /* lower portion for support of 64 cores */
211 u8 res_09c[0xa0-0x9c];
212 u32 pvr; /* Processor version */
213 u32 svr; /* System version */
214 u32 mvr; /* Manufacturing version */
215 u8 res_0ac[0xb0-0xac];
216 u32 rstcr; /* Reset control */
217 u32 rstrqpblsr; /* Reset request preboot loader status */
218 u8 res_0b8[0xc0-0xb8];
219 u32 rstrqmr1; /* Reset request mask */
220 u8 res_0c4[0xc8-0xc4];
221 u32 rstrqsr1; /* Reset request status */
222 u8 res_0cc[0xd4-0xcc];
223 u32 rstrqwdtmrl; /* Reset request WDT mask */
224 u8 res_0d8[0xdc-0xd8];
225 u32 rstrqwdtsrl; /* Reset request WDT status */
226 u8 res_0e0[0xe4-0xe0];
227 u32 brrl; /* Boot release */
228 u8 res_0e8[0x100-0xe8];
229 u32 rcwsr[16]; /* Reset control word status */
241 u8 res_140[0x200-0x140];
242 u32 scratchrw[4]; /* Scratch Read/Write */
243 u8 res_210[0x300-0x210];
244 u32 scratchw1r[4]; /* Scratch Read (Write once) */
245 u8 res_310[0x400-0x310];
246 u32 crstsr[12];
247 u8 res_430[0x500-0x430];
250 u32 dcfg_ccsr_pex1liodnr;
251 u32 dcfg_ccsr_pex2liodnr;
252 u32 dcfg_ccsr_pex3liodnr;
253 u32 dcfg_ccsr_pex4liodnr;
255 u32 dcfg_ccsr_rio1liodnr;
256 u32 dcfg_ccsr_rio2liodnr;
257 u32 dcfg_ccsr_rio3liodnr;
258 u32 dcfg_ccsr_rio4liodnr;
260 u32 dcfg_ccsr_usb1liodnr;
261 u32 dcfg_ccsr_usb2liodnr;
262 u32 dcfg_ccsr_usb3liodnr;
263 u32 dcfg_ccsr_usb4liodnr;
265 u32 dcfg_ccsr_sdmmc1liodnr;
266 u32 dcfg_ccsr_sdmmc2liodnr;
267 u32 dcfg_ccsr_sdmmc3liodnr;
268 u32 dcfg_ccsr_sdmmc4liodnr;
270 u32 dcfg_ccsr_riomaintliodnr;
272 u8 res_544[0x550-0x544];
273 u32 sataliodnr[4];
274 u8 res_560[0x570-0x560];
276 u32 dcfg_ccsr_misc1liodnr;
277 u32 dcfg_ccsr_misc2liodnr;
278 u32 dcfg_ccsr_misc3liodnr;
279 u32 dcfg_ccsr_misc4liodnr;
280 u32 dcfg_ccsr_dma1liodnr;
281 u32 dcfg_ccsr_dma2liodnr;
282 u32 dcfg_ccsr_dma3liodnr;
283 u32 dcfg_ccsr_dma4liodnr;
284 u32 dcfg_ccsr_spare1liodnr;
285 u32 dcfg_ccsr_spare2liodnr;
286 u32 dcfg_ccsr_spare3liodnr;
287 u32 dcfg_ccsr_spare4liodnr;
288 u8 res_5a0[0x600-0x5a0];
289 u32 dcfg_ccsr_pblsr;
291 u32 pamubypenr;
292 u32 dmacr1;
294 u8 res_60c[0x610-0x60c];
295 u32 dcfg_ccsr_gensr1;
296 u32 dcfg_ccsr_gensr2;
297 u32 dcfg_ccsr_gensr3;
298 u32 dcfg_ccsr_gensr4;
299 u32 dcfg_ccsr_gencr1;
300 u32 dcfg_ccsr_gencr2;
301 u32 dcfg_ccsr_gencr3;
302 u32 dcfg_ccsr_gencr4;
303 u32 dcfg_ccsr_gencr5;
304 u32 dcfg_ccsr_gencr6;
305 u32 dcfg_ccsr_gencr7;
306 u8 res_63c[0x658-0x63c];
307 u32 dcfg_ccsr_cgensr1;
308 u32 dcfg_ccsr_cgensr0;
309 u8 res_660[0x678-0x660];
310 u32 dcfg_ccsr_cgencr1;
312 u32 dcfg_ccsr_cgencr0;
313 u8 res_680[0x700-0x680];
314 u32 dcfg_ccsr_sriopstecr;
315 u32 dcfg_ccsr_dcsrcr;
317 u8 res_708[0x740-0x708]; /* add more registers when needed */
318 u32 tp_ityp[64]; /* Topology Initiator Type Register */
319 struct {
322 } tp_cluster[16];
323 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
324 u32 dcfg_ccsr_qmbm_warmrst;
325 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
326 u32 dcfg_ccsr_reserved0;
327 u32 dcfg_ccsr_reserved1;