38 #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)  argument
104 					int cpu)  in sunxi_power_switch()  argument
111 		clrbits_le32(pwroff, BIT(cpu));  in sunxi_power_switch()
114 		setbits_le32(pwroff, BIT(cpu));  in sunxi_power_switch()
140 static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)  in sunxi_cpu_set_power()  argument
149 static void __secure sunxi_cpu_set_power(int cpu, bool on)  in sunxi_cpu_set_power()  argument
154 	sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),  in sunxi_cpu_set_power()
159 static void __secure sunxi_cpu_set_power(int cpu, bool on)  in sunxi_cpu_set_power()  argument
164 	sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,  in sunxi_cpu_set_power()
165 			   on, cpu);  in sunxi_cpu_set_power()
173 	u32 cpu = cpuid & 0x3;  in sunxi_cpu_power_off()  local
177 		if (readl(&cpucfg->cpu[cpu].status) & BIT(2))  in sunxi_cpu_power_off()
183 	writel(0, &cpucfg->cpu[cpu].rst);  in sunxi_cpu_power_off()
186 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in sunxi_cpu_power_off()
192 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in sunxi_cpu_power_off()
218 	u32 scr, reg, cpu;  in psci_fiq_enter()  local
236 	cpu = (reg >> 10) & 0x7;  in psci_fiq_enter()
239 	sunxi_cpu_power_off(cpu);  in psci_fiq_enter()
250 	u32 cpu = (mpidr & 0x3);  in psci_cpu_on()  local
253 	psci_save_target_pc(cpu, pc);  in psci_cpu_on()
259 	writel(0, &cpucfg->cpu[cpu].rst);  in psci_cpu_on()
262 	clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));  in psci_cpu_on()
265 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in psci_cpu_on()
268 	sunxi_cpu_set_power(cpu, true);  in psci_cpu_on()
271 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);  in psci_cpu_on()
274 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));  in psci_cpu_on()