46 	static uint32_t ver;  in zynqmp_get_silicon_ver()  local
48 	if (ver == 0U) {  in zynqmp_get_silicon_ver()
49 		ver = mmio_read_32(ZYNQMP_CSU_BASEADDR +  in zynqmp_get_silicon_ver()
51 		ver &= ZYNQMP_SILICON_VER_MASK;  in zynqmp_get_silicon_ver()
52 		ver >>= ZYNQMP_SILICON_VER_SHIFT;  in zynqmp_get_silicon_ver()
55 	return ver;  in zynqmp_get_silicon_ver()
60 	unsigned int ver = zynqmp_get_silicon_ver();  in get_uart_clk()  local
63 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {  in get_uart_clk()
76 	uint16_t ver;  member
85 		.ver = 0x2c,
94 		.ver = 0x2c,
104 		.ver = 0x100,
110 		.ver = 0x12c,
120 		.ver = 0x100,
126 		.ver = 0x12c,
136 		.ver = 0x100,
142 		.ver = 0x12c,
151 		.ver = 0x2c,
160 		.ver = 0x2c,
238 	uint32_t id, ver, chipid[2];  in zynqmp_get_silicon_idcode_name()  local
249 	ver = chipid[1] >> ZYNQMP_EFUSE_IPDISABLE_SHIFT;  in zynqmp_get_silicon_idcode_name()
253 		    (zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))) {  in zynqmp_get_silicon_idcode_name()
273 	if ((ver & ZYNQMP_PL_STATUS_MASK) != 0U) {  in zynqmp_get_silicon_idcode_name()
289 	uint32_t ver;  in zynqmp_get_rtl_ver()  local
291 	ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);  in zynqmp_get_rtl_ver()
292 	ver &= ZYNQMP_RTL_VER_MASK;  in zynqmp_get_rtl_ver()
293 	ver >>= ZYNQMP_RTL_VER_SHIFT;  in zynqmp_get_rtl_ver()
295 	return ver;  in zynqmp_get_rtl_ver()
348 	uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET);  in zynqmp_get_ps_ver()  local
350 	ver &= ZYNQMP_PS_VER_MASK;  in zynqmp_get_ps_ver()
351 	ver >>= ZYNQMP_PS_VER_SHIFT;  in zynqmp_get_ps_ver()
353 	return ver + 1U;  in zynqmp_get_ps_ver()
358 	uint32_t ver = zynqmp_get_silicon_ver();  in zynqmp_print_platform_name()  local
362 	switch (ver) {  in zynqmp_print_platform_name()
407 	uint32_t ver = zynqmp_get_silicon_ver();  in plat_get_syscnt_freq2()  local
410 	if (ver == ZYNQMP_CSU_VERSION_QEMU) {  in plat_get_syscnt_freq2()