72 static inline uintptr_t a3700_rdist_base(unsigned int proc)  in a3700_rdist_base()  argument
74 	return PLAT_MARVELL_GICR_BASE + (proc << GICR_V3_PCPUBASE_SHIFT);  in a3700_rdist_base()
77 static inline uint32_t a3700_gicr_read(unsigned int proc, uint32_t reg)  in a3700_gicr_read()  argument
79 	return mmio_read_32(a3700_rdist_base(proc) + reg);  in a3700_gicr_read()
82 static inline void a3700_gicr_write(unsigned int proc, uint32_t reg,  in a3700_gicr_write()  argument
85 	mmio_write_32(a3700_rdist_base(proc) + reg, value);  in a3700_gicr_write()
88 static void a3700_gic_redist_disable_irqs(unsigned int proc)  in a3700_gic_redist_disable_irqs()  argument
90 	a3700_gicr_write(proc, GICR_ICENABLER0, GENMASK_32(31, 0));  in a3700_gic_redist_disable_irqs()
93 	if ((a3700_gicr_read(proc, GICR_CTLR) & GICR_CTLR_RWP_BIT) != 0U) {  in a3700_gic_redist_disable_irqs()
94 		ERROR("could not disable core %u PPIs & SGIs\n", proc);  in a3700_gic_redist_disable_irqs()
98 static void a3700_gic_redist_mark_asleep(unsigned int proc)  in a3700_gic_redist_mark_asleep()  argument
100 	a3700_gicr_write(proc, GICR_WAKER,  in a3700_gic_redist_mark_asleep()
101 			 a3700_gicr_read(proc, GICR_WAKER) | WAKER_PS_BIT);  in a3700_gic_redist_mark_asleep()
104 	if ((a3700_gicr_read(proc, GICR_WAKER) & WAKER_CA_BIT) == 0U) {  in a3700_gic_redist_mark_asleep()
105 		ERROR("could not mark core %u redistributor asleep\n", proc);  in a3700_gic_redist_mark_asleep()