108 static void imx_gpc_hwirq_mask(unsigned int hwirq)  in imx_gpc_hwirq_mask()  argument
113 	if (hwirq >= MAX_HW_IRQ_NUM) {  in imx_gpc_hwirq_mask()
118 	reg = gpc_imr_offset[0] + (hwirq / 32) * 4;  in imx_gpc_hwirq_mask()
120 	val |= 1 << hwirq % 32;  in imx_gpc_hwirq_mask()
125 static void imx_gpc_hwirq_unmask(unsigned int hwirq)  in imx_gpc_hwirq_unmask()  argument
130 	if (hwirq >= MAX_HW_IRQ_NUM) {  in imx_gpc_hwirq_unmask()
135 	reg = gpc_imr_offset[0] + (hwirq / 32) * 4;  in imx_gpc_hwirq_unmask()
137 	val &= ~(1 << hwirq % 32);  in imx_gpc_hwirq_unmask()
142 static void imx_gpc_set_wake(uint32_t hwirq, bool on)  in imx_gpc_set_wake()  argument
146 	if (hwirq >= MAX_HW_IRQ_NUM) {  in imx_gpc_set_wake()
150 	mask = 1 << hwirq % 32;  in imx_gpc_set_wake()
151 	idx = hwirq / 32;  in imx_gpc_set_wake()
183 static void imx_gpc_set_affinity(uint32_t hwirq, unsigned int cpu_idx)  in imx_gpc_set_affinity()  argument
188 	if (hwirq >= MAX_HW_IRQ_NUM || cpu_idx >= 4) {  in imx_gpc_set_affinity()
197 	reg = gpc_imr_offset[cpu_idx] + (hwirq / 32) * 4;  in imx_gpc_set_affinity()
199 	val &= ~(1 << hwirq % 32);  in imx_gpc_set_affinity()
207 			reg = gpc_imr_offset[i] + (hwirq / 32) * 4;  in imx_gpc_set_affinity()
209 			val |= (1 << hwirq % 32);  in imx_gpc_set_affinity()