73 void vpu_sft_reset_assert(uint32_t domain_id)  in vpu_sft_reset_assert()  argument
79 	switch (domain_id) {  in vpu_sft_reset_assert()
97 void vpu_sft_reset_deassert(uint32_t domain_id)  in vpu_sft_reset_deassert()  argument
103 	switch (domain_id) {  in vpu_sft_reset_deassert()
121 void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on)  in imx_gpc_pm_domain_enable()  argument
123 	if (domain_id >= MAX_DOMAINS) {  in imx_gpc_pm_domain_enable()
127 	struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id];  in imx_gpc_pm_domain_enable()
130 		pu_domain_status |= (1 << domain_id);  in imx_gpc_pm_domain_enable()
132 		if (domain_id == VPU_G1 || domain_id == VPU_G2 ||  in imx_gpc_pm_domain_enable()
133 		    domain_id == VPU_H1) {  in imx_gpc_pm_domain_enable()
134 			vpu_sft_reset_assert(domain_id);  in imx_gpc_pm_domain_enable()
138 		if (domain_id != HSIOMIX) {  in imx_gpc_pm_domain_enable()
151 		if (domain_id == VPU_G1 || domain_id == VPU_G2 ||  in imx_gpc_pm_domain_enable()
152 		    domain_id == VPU_H1) {  in imx_gpc_pm_domain_enable()
153 			vpu_sft_reset_deassert(domain_id);  in imx_gpc_pm_domain_enable()
158 		if (domain_id == GPUMIX) {  in imx_gpc_pm_domain_enable()
191 		if (domain_id == VPUMIX) {  in imx_gpc_pm_domain_enable()
201 		if (domain_id == DISPMIX) {  in imx_gpc_pm_domain_enable()
219 		if (domain_id == GPUMIX) {  in imx_gpc_pm_domain_enable()
237 		pu_domain_status &= ~(1 << domain_id);  in imx_gpc_pm_domain_enable()
239 		if (domain_id == OTG1 || domain_id == OTG2) {  in imx_gpc_pm_domain_enable()
244 		if (domain_id == GPUMIX) {  in imx_gpc_pm_domain_enable()
271 		if (domain_id == GPUMIX) {  in imx_gpc_pm_domain_enable()
294 		if (domain_id != HSIOMIX) {  in imx_gpc_pm_domain_enable()