118 static uintptr_t qspi_base(void)  in qspi_base()  function
127 	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) {  in stm32_qspi_wait_for_not_busy()
143 	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) {  in stm32_qspi_wait_cmd()
151 		if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) {  in stm32_qspi_wait_cmd()
160 	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF);  in stm32_qspi_wait_cmd()
196 		while ((mmio_read_32(qspi_base() + QSPI_SR) &  in stm32_qspi_poll()
204 		fifo(buf++, qspi_base() + QSPI_DR);  in stm32_qspi_poll()
266 		mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U);  in stm32_qspi_exec_op()
289 	mmio_write_32(qspi_base() + QSPI_CCR, ccr);  in stm32_qspi_exec_op()
292 		mmio_write_32(qspi_base() + QSPI_AR, op->addr.val);  in stm32_qspi_exec_op()
317 	mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT);  in stm32_qspi_exec_op()
321 	while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) {  in stm32_qspi_exec_op()
328 	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF);  in stm32_qspi_exec_op()
351 	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr);  in stm32_qspi_claim_bus()
358 	mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN);  in stm32_qspi_release_bus()
387 	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK,  in stm32_qspi_set_speed()
390 	mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht);  in stm32_qspi_set_speed()
411 		mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);  in stm32_qspi_set_mode()
413 		mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);  in stm32_qspi_set_mode()
504 	mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT);  in stm32_qspi_init()
505 	mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK);  in stm32_qspi_init()