2671 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)  in clk_stm32_load_vco_config()  argument
2675 	err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, &pll->cfg[PLLCFG_M]);  in clk_stm32_load_vco_config()
2680 	err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg);  in clk_stm32_load_vco_config()
2691 	pll->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);  in clk_stm32_load_vco_config()
2693 	pll->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);  in clk_stm32_load_vco_config()
2698 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)  in clk_stm32_load_output_config()  argument
2702 	err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB,  in clk_stm32_load_output_config()
2713 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll)  in clk_stm32_parse_pll_fdt()  argument
2720 	cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);  in clk_stm32_parse_pll_fdt()
2761 		int subnode;  in stm32_clk_parse_fdt_all_pll()  local
2766 		subnode = fdt_subnode_offset(fdt, node, name);  in stm32_clk_parse_fdt_all_pll()
2767 		if (!fdt_check_node(subnode)) {  in stm32_clk_parse_fdt_all_pll()
2771 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);  in stm32_clk_parse_fdt_all_pll()