st/clk/stm32mp1_clk.c

161 #define MUX_CFG(_id, _offset, _shift, _width)\  macro
165 	MUX_CFG(MUX_PLL12,	RCC_RCK12SELR, 0, 2),
166 	MUX_CFG(MUX_PLL3,	RCC_RCK3SELR, 0, 2),
167 	MUX_CFG(MUX_PLL4,	RCC_RCK4SELR, 0, 2),
168 	MUX_CFG(MUX_CKPER,	RCC_CPERCKSELR, 0, 2),
172 	MUX_CFG(MUX_RTC,	RCC_BDCR, 16, 2),
173 	MUX_CFG(MUX_SDMMC12,	RCC_SDMMC12CKSELR, 0, 3),
174 	MUX_CFG(MUX_SPI2S23,	RCC_SPI2S23CKSELR, 0, 3),
175 	MUX_CFG(MUX_SPI45,	RCC_SPI45CKSELR, 0, 3),
176 	MUX_CFG(MUX_I2C12,	RCC_I2C12CKSELR, 0, 3),
177 	MUX_CFG(MUX_I2C35,	RCC_I2C35CKSELR, 0, 3),
178 	MUX_CFG(MUX_LPTIM23,	RCC_LPTIM23CKSELR, 0, 3),
179 	MUX_CFG(MUX_LPTIM45,	RCC_LPTIM45CKSELR, 0, 3),
180 	MUX_CFG(MUX_UART24,	RCC_UART24CKSELR, 0, 3),
181 	MUX_CFG(MUX_UART35,	RCC_UART35CKSELR, 0, 3),
182 	MUX_CFG(MUX_UART78,	RCC_UART78CKSELR, 0, 3),
183 	MUX_CFG(MUX_SAI1,	RCC_SAI1CKSELR, 0, 3),
184 	MUX_CFG(MUX_ETH,	RCC_ETHCKSELR, 0, 2),
185 	MUX_CFG(MUX_I2C46,	RCC_I2C46CKSELR, 0, 3),
186 	MUX_CFG(MUX_RNG2,	RCC_RNG2CKSELR, 0, 2),
187 	MUX_CFG(MUX_SDMMC3,	RCC_SDMMC3CKSELR, 0, 3),
188 	MUX_CFG(MUX_FMC,	RCC_FMCCKSELR, 0, 2),
189 	MUX_CFG(MUX_QSPI,	RCC_QSPICKSELR, 0, 2),
190 	MUX_CFG(MUX_USBPHY,	RCC_USBCKSELR, 0, 2),
191 	MUX_CFG(MUX_USBO,	RCC_USBCKSELR, 4, 1),
192 	MUX_CFG(MUX_SPDIF,	RCC_SPDIFCKSELR, 0, 2),
193 	MUX_CFG(MUX_SPI2S1,	RCC_SPI2S1CKSELR, 0, 3),
194 	MUX_CFG(MUX_CEC,	RCC_CECCKSELR, 0, 2),
195 	MUX_CFG(MUX_LPTIM1,	RCC_LPTIM1CKSELR, 0, 3),
196 	MUX_CFG(MUX_UART6,	RCC_UART6CKSELR, 0, 3),
197 	MUX_CFG(MUX_FDCAN,	RCC_FDCANCKSELR, 0, 2),
198 	MUX_CFG(MUX_SAI2,	RCC_SAI2CKSELR, 0, 3),
199 	MUX_CFG(MUX_SAI3,	RCC_SAI3CKSELR, 0, 3),
200 	MUX_CFG(MUX_SAI4,	RCC_SAI4CKSELR, 0, 3),
201 	MUX_CFG(MUX_ADC,	RCC_ADCCKSELR, 0, 2),
202 	MUX_CFG(MUX_DSI,	RCC_DSICKSELR, 0, 1),
203 	MUX_CFG(MUX_RNG1,	RCC_RNG1CKSELR, 0, 2),
204 	MUX_CFG(MUX_STGEN,	RCC_STGENCKSELR, 0, 2),
205 	MUX_CFG(MUX_UART1,	RCC_UART1CKSELR, 0, 3),
206 	MUX_CFG(MUX_SPI6,	RCC_SPI6CKSELR, 0, 3),
207 	MUX_CFG(MUX_MCO1,	RCC_MCO1CFGR, 0, 3),
208 	MUX_CFG(MUX_MCO2,	RCC_MCO2CFGR, 0, 3),