735 static unsigned long clk_get_pll_fvco(struct stm32_clk_priv *priv,  in clk_get_pll_fvco()  argument
741 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_get_pll_fvco()
770 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_is_enabled()  argument
772 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_is_enabled()
777 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_on()  argument
779 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_on()
784 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_set_off()  argument
786 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_set_off()
792 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv,  in _clk_stm32_pll_wait_ready_on()  argument
795 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_on()
811 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv,  in _clk_stm32_pll_wait_ready_off()  argument
814 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_wait_ready_off()
829 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_enable()  argument
831 	if (_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_enable()
835 	_clk_stm32_pll_set_on(priv, pll);  in _clk_stm32_pll_enable()
837 	return _clk_stm32_pll_wait_ready_on(priv, pll);  in _clk_stm32_pll_enable()
840 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll)  in _clk_stm32_pll_disable()  argument
842 	if (!_clk_stm32_pll_is_enabled(priv, pll)) {  in _clk_stm32_pll_disable()
846 	_clk_stm32_pll_set_off(priv, pll);  in _clk_stm32_pll_disable()
848 	_clk_stm32_pll_wait_ready_off(priv, pll);  in _clk_stm32_pll_disable()
851 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_is_enabled()  argument
853 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_is_enabled()
857 	return _clk_stm32_pll_is_enabled(priv, pll);  in clk_stm32_pll_is_enabled()
860 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_enable()  argument
862 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_enable()
866 	return _clk_stm32_pll_enable(priv, pll);  in clk_stm32_pll_enable()
869 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id)  in clk_stm32_pll_disable()  argument
871 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_disable()
875 	_clk_stm32_pll_disable(priv, pll);  in clk_stm32_pll_disable()
878 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id,  in clk_stm32_pll_recalc_rate()  argument
881 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_stm32_pll_recalc_rate()
884 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_recalc_rate()
900 			dfout = clk_get_pll_fvco(priv, pll, prate) / (postdiv1 * postdiv2);  in clk_stm32_pll_recalc_rate()
937 static unsigned long clk_stm32_pll1_recalc_rate(struct stm32_clk_priv *priv,  in clk_stm32_pll1_recalc_rate()  argument
976 static unsigned long clk_flexgen_recalc(struct stm32_clk_priv *priv, int idx,  in clk_flexgen_recalc()  argument
979 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_flexgen_recalc()
981 	uintptr_t rcc_base = priv->base;  in clk_flexgen_recalc()
1014 static int clk_flexgen_get_parent(struct stm32_clk_priv *priv, int idx)  in clk_flexgen_get_parent()  argument
1016 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_flexgen_get_parent()
1020 	uintptr_t rcc_base = priv->base;  in clk_flexgen_get_parent()
1029 static int clk_flexgen_gate_enable(struct stm32_clk_priv *priv, int idx)  in clk_flexgen_gate_enable()  argument
1031 	const struct clk_stm32 *clk = _clk_get(priv, idx);  in clk_flexgen_gate_enable()
1033 	uintptr_t rcc_base = priv->base;  in clk_flexgen_gate_enable()
1042 static void clk_flexgen_gate_disable(struct stm32_clk_priv *priv, int id)  in clk_flexgen_gate_disable()  argument
1044 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_flexgen_gate_disable()
1046 	uintptr_t rcc_base = priv->base;  in clk_flexgen_gate_disable()
1053 static bool clk_flexgen_gate_is_enabled(struct stm32_clk_priv *priv, int id)  in clk_flexgen_gate_is_enabled()  argument
1055 	const struct clk_stm32 *clk = _clk_get(priv, id);  in clk_flexgen_gate_is_enabled()
1057 	uintptr_t rcc_base = priv->base;  in clk_flexgen_gate_is_enabled()
1088 static int clk_stm32_osc_msi_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate,  in clk_stm32_osc_msi_set_rate()  argument
1091 	uintptr_t address = priv->base + RCC_BDCR;  in clk_stm32_osc_msi_set_rate()
1115 static unsigned long clk_stm32_osc_msi_recalc_rate(struct stm32_clk_priv *priv,  in clk_stm32_osc_msi_recalc_rate()  argument
1122 	uintptr_t address = priv->base + RCC_BDCR;  in clk_stm32_osc_msi_recalc_rate()
1538 static void stm32mp2_clk_muxsel_on_hsi(struct stm32_clk_priv *priv)  in stm32mp2_clk_muxsel_on_hsi()  argument
1540 	mmio_clrbits_32(priv->base + RCC_MUXSELCFGR,  in stm32mp2_clk_muxsel_on_hsi()
1551 static void stm32mp2_clk_xbar_on_hsi(struct stm32_clk_priv *priv)  in stm32mp2_clk_xbar_on_hsi()  argument
1553 	uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR;  in stm32mp2_clk_xbar_on_hsi()
1624 static int clk_stm32_pll_config_output(struct stm32_clk_priv *priv,  in clk_stm32_pll_config_output()  argument
1629 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()
1637 	refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in clk_stm32_pll_config_output()
1696 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv,  in clk_stm32_pll_config_csg()  argument
1700 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()
1727 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data);
1731 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in clk_stm32_pll_get_pdata()  local
1732 	struct stm32_clk_platdata *pdata = priv->pdata;  in clk_stm32_pll_get_pdata()
1737 static int _clk_stm32_pll1_init(struct stm32_clk_priv *priv, int pll_idx,  in _clk_stm32_pll1_init()  argument
1746 	ret = stm32_clk_configure_mux(priv, pll_conf->src);  in _clk_stm32_pll1_init()
1751 	refclk = _clk_stm32_get_parent_rate(priv, pll->clk_id);  in _clk_stm32_pll1_init()
1773 static int clk_stm32_pll_wait_mux_ready(struct stm32_clk_priv *priv,  in clk_stm32_pll_wait_mux_ready()  argument
1776 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_wait_mux_ready()
1790 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx,  in _clk_stm32_pll_init()  argument
1794 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in _clk_stm32_pll_init()
1798 	_clk_stm32_pll_disable(priv, pll);  in _clk_stm32_pll_init()
1800 	ret = stm32_clk_configure_mux(priv, pll_conf->src);  in _clk_stm32_pll_init()
1805 	ret = clk_stm32_pll_wait_mux_ready(priv, pll);  in _clk_stm32_pll_init()
1810 	ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac);  in _clk_stm32_pll_init()
1816 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in _clk_stm32_pll_init()
1820 	_clk_stm32_pll_enable(priv, pll);  in _clk_stm32_pll_init()
1829 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx)  in clk_stm32_pll_init()  argument
1835 			return _clk_stm32_pll1_init(priv, pll_idx, pll_conf);  in clk_stm32_pll_init()
1837 			return _clk_stm32_pll_init(priv, pll_idx, pll_conf);  in clk_stm32_pll_init()
1844 static int stm32mp2_clk_pll_configure(struct stm32_clk_priv *priv)  in stm32mp2_clk_pll_configure()  argument
1855 		err = clk_stm32_pll_init(priv, i);  in stm32mp2_clk_pll_configure()
1866 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in wait_predivsr()  local
1867 	uintptr_t rcc_base = priv->base;  in wait_predivsr()
1894 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in wait_findivsr()  local
1895 	uintptr_t rcc_base = priv->base;  in wait_findivsr()
1922 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in wait_xbar_sts()  local
1923 	uintptr_t rcc_base = priv->base;  in wait_xbar_sts()
1942 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in flexclkgen_config_channel()  local
1943 	uintptr_t rcc_base = priv->base;  in flexclkgen_config_channel()
1984 static int stm32mp2_clk_flexgen_configure(struct stm32_clk_priv *priv)  in stm32mp2_clk_flexgen_configure()  argument
1986 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32mp2_clk_flexgen_configure()
2019 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv)  in stm32_enable_oscillator_hse()  argument
2021 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_enable_oscillator_hse()
2027 	if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) {  in stm32_enable_oscillator_hse()
2031 	clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass);  in stm32_enable_oscillator_hse()
2033 	_clk_stm32_enable(priv, _CK_HSE);  in stm32_enable_oscillator_hse()
2035 	clk_oscillator_set_css(priv, _CK_HSE, css);  in stm32_enable_oscillator_hse()
2038 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv)  in stm32_enable_oscillator_lse()  argument
2040 	struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE);  in stm32_enable_oscillator_lse()
2041 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_enable_oscillator_lse()
2047 	if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) {  in stm32_enable_oscillator_lse()
2052 	if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) {  in stm32_enable_oscillator_lse()
2056 	clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass);  in stm32_enable_oscillator_lse()
2058 	clk_oscillator_set_drive(priv, _CK_LSE, drive);  in stm32_enable_oscillator_lse()
2060 	_clk_stm32_gate_enable(priv, osc_data->gate_id);  in stm32_enable_oscillator_lse()
2063 static int stm32mp2_clk_switch_to_hsi(struct stm32_clk_priv *priv)  in stm32mp2_clk_switch_to_hsi()  argument
2066 	stm32mp2_clk_muxsel_on_hsi(priv);  in stm32mp2_clk_switch_to_hsi()
2067 	stm32mp2_clk_xbar_on_hsi(priv);  in stm32mp2_clk_switch_to_hsi()
2072 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv)  in stm32_clk_oscillators_wait_lse_ready()  argument
2076 	if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) {  in stm32_clk_oscillators_wait_lse_ready()
2077 		ret = clk_oscillator_wait_ready_on(priv, _CK_LSE);  in stm32_clk_oscillators_wait_lse_ready()
2083 static void stm32_enable_oscillator_msi(struct stm32_clk_priv *priv)  in stm32_enable_oscillator_msi()  argument
2086 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_enable_oscillator_msi()
2090 	err = clk_stm32_osc_msi_set_rate(priv, _CK_MSI, osci->freq, 0);  in stm32_enable_oscillator_msi()
2098 	_clk_stm32_enable(priv, _CK_MSI);  in stm32_enable_oscillator_msi()
2101 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv)  in stm32_clk_oscillators_enable()  argument
2103 	stm32_enable_oscillator_hse(priv);  in stm32_clk_oscillators_enable()
2104 	stm32_enable_oscillator_lse(priv);  in stm32_clk_oscillators_enable()
2105 	stm32_enable_oscillator_msi(priv);  in stm32_clk_oscillators_enable()
2106 	_clk_stm32_enable(priv, _CK_LSI);  in stm32_clk_oscillators_enable()
2109 static int stm32_clk_configure_div(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_div()  argument
2114 	return clk_stm32_set_div(priv, div_id, div_n);  in stm32_clk_configure_div()
2117 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_mux()  argument
2122 	return clk_mux_set_parent(priv, mux_id, sel);  in stm32_clk_configure_mux()
2125 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_clk_get_binding_id()  argument
2129 	return clk_get_index(priv, binding_id);  in stm32_clk_configure_clk_get_binding_id()
2132 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data)  in stm32_clk_configure_clk()  argument
2139 	clk_id = stm32_clk_configure_clk_get_binding_id(priv, data);  in stm32_clk_configure_clk()
2145 		ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel);  in stm32_clk_configure_clk()
2152 		clk_stm32_enable_call_ops(priv, clk_id);  in stm32_clk_configure_clk()
2154 		clk_stm32_disable_call_ops(priv, clk_id);  in stm32_clk_configure_clk()
2160 static int stm32_clk_configure(struct stm32_clk_priv *priv, uint32_t val)  in stm32_clk_configure()  argument
2168 		ret = stm32_clk_configure_div(priv, cmd_data);  in stm32_clk_configure()
2172 		ret = stm32_clk_configure_mux(priv, cmd_data);  in stm32_clk_configure()
2176 		ret = stm32_clk_configure_clk(priv, cmd_data);  in stm32_clk_configure()
2187 static int stm32_clk_bus_configure(struct stm32_clk_priv *priv)  in stm32_clk_bus_configure()  argument
2189 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_clk_bus_configure()
2195 		ret = stm32_clk_configure(priv, pdata->busclk[i]);  in stm32_clk_bus_configure()
2204 static int stm32_clk_kernel_configure(struct stm32_clk_priv *priv)  in stm32_clk_kernel_configure()  argument
2206 	struct stm32_clk_platdata *pdata = priv->pdata;  in stm32_clk_kernel_configure()
2212 		ret = stm32_clk_configure(priv, pdata->kernelclk[i]);  in stm32_clk_kernel_configure()
2223 	struct stm32_clk_priv *priv = clk_stm32_get_priv();  in stm32mp2_init_clock_tree()  local
2230 	stm32_clk_oscillators_enable(priv);  in stm32mp2_init_clock_tree()
2233 	ret = stm32mp2_clk_switch_to_hsi(priv);  in stm32mp2_init_clock_tree()
2238 	ret = stm32mp2_clk_pll_configure(priv);  in stm32mp2_init_clock_tree()
2244 	ret = stm32_clk_oscillators_wait_lse_ready(priv);  in stm32mp2_init_clock_tree()
2249 	ret = stm32mp2_clk_flexgen_configure(priv);  in stm32mp2_init_clock_tree()
2254 	ret = stm32_clk_bus_configure(priv);  in stm32mp2_init_clock_tree()
2259 	ret = stm32_clk_kernel_configure(priv);  in stm32mp2_init_clock_tree()