1738 				struct stm32_pll_dt_cfg *pll_conf)  in _clk_stm32_pll1_init()  argument
1746 	ret = stm32_clk_configure_mux(priv, pll_conf->src);  in _clk_stm32_pll1_init()
1762 	stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], pll_conf->cfg[REFDIV],  in _clk_stm32_pll1_init()
1763 				 pll_conf->cfg[POSTDIV1], pll_conf->cfg[POSTDIV2]);  in _clk_stm32_pll1_init()
1791 			       struct stm32_pll_dt_cfg *pll_conf)  in _clk_stm32_pll_init()  argument
1800 	ret = stm32_clk_configure_mux(priv, pll_conf->src);  in _clk_stm32_pll_init()
1810 	ret = clk_stm32_pll_config_output(priv, pll, pll_conf->cfg, pll_conf->frac);  in _clk_stm32_pll_init()
1815 	if (pll_conf->csg_enabled) {  in _clk_stm32_pll_init()
1816 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in _clk_stm32_pll_init()
1831 	struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx);  in clk_stm32_pll_init()  local
1833 	if (pll_conf->enabled) {  in clk_stm32_pll_init()
1835 			return _clk_stm32_pll1_init(priv, pll_idx, pll_conf);  in clk_stm32_pll_init()
1837 			return _clk_stm32_pll_init(priv, pll_idx, pll_conf);  in clk_stm32_pll_init()