1498 	uintptr_t a35_ss_address = A35SSC_BASE;  in stm32mp2_a35_ss_on_hsi()  local
1499 	uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;  in stm32mp2_a35_ss_on_hsi()
1500 	uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;  in stm32mp2_a35_ss_on_hsi()
1565 	uintptr_t a35_ss_address = A35SSC_BASE;  in stm32mp2_a35_pll1_start()  local
1566 	uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;  in stm32mp2_a35_pll1_start()
1567 	uintptr_t chgclkreq_reg = a35_ss_address + A35_SS_CHGCLKREQ;  in stm32mp2_a35_pll1_start()
1603 	uintptr_t a35_ss_address = A35SSC_BASE;  in stm32mp2_a35_pll1_config()  local
1604 	uintptr_t pll_freq1_reg = a35_ss_address + A35_SS_PLL_FREQ1;  in stm32mp2_a35_pll1_config()
1605 	uintptr_t pll_freq2_reg = a35_ss_address + A35_SS_PLL_FREQ2;  in stm32mp2_a35_pll1_config()
2555 	uintptr_t a35_ss_address = A35SSC_BASE;  in stm32mp2_pll1_disable()
2556 	uintptr_t pll_enable_reg = a35_ss_address + A35_SS_PLL_ENABLE;  in stm32mp2_pll1_disable()