609 	config_pll_out_div(pll_addr, pdiv->index, dc);  in enable_pll_div()
699 	return cgm_mux_clk_config(cgm_addr, mux->index,  in enable_cgm_mux()
715 		      mux->source_id, mux->index);  in get_mux_parent()
743 		      mux->source_id, mux->index);  in enable_mux()
990 	return init_dfs_port(dfs_addr, dfs_div->index, mfi, mfn);  in enable_dfs_div()
1172 		      cgm_div->index);  in enable_cgm_div()
1192 		      mux->index, cgm_addr);  in enable_cgm_div()
1202 		mux->index, cgm_div->index, (unsigned long)pfreq,  in enable_cgm_div()
1207 	cgm_mux_div_config(cgm_addr, mux->index, dc - 1U, cgm_div->index);  in enable_cgm_div()
1289 	if (!is_cgm_div_enabled(cgm_addr, mux->index, cgm_div->index)) {  in get_cgm_div_freq()
1297 		      mux->index, cgm_addr);  in get_cgm_div_freq()
1301 	*rate = calc_cgm_div_freq(cgm_addr, mux->index, cgm_div->index, pfreq);  in get_cgm_div_freq()
1380 	uint32_t index;  in enable_module()  local
1392 	index = (uint32_t)module->type;  in enable_module()
1394 	if (index >= ARRAY_SIZE(enable_clbs)) {  in enable_module()
1399 	if (enable_clbs[index] == NULL) {  in enable_module()
1413 	ret = exec_cb_with_refcount(enable_clbs[index], module, drv,  in enable_module()
1738 	pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index));  in get_pll_div_freq()
1814 		      mux->index, mux->source_id);  in set_mux_freq()
1837 		      mux->index, mux->source_id);  in get_mux_freq()
1930 	dvport = mmio_read_32(DFS_DVPORTn(dfs_addr, dfs_div->index));  in get_dfs_div_freq()
2156 	uint32_t index;  in get_module_parent()  local
2162 	index = (uint32_t)module->type;  in get_module_parent()
2164 	if (index >= ARRAY_SIZE(parents_clbs)) {  in get_module_parent()
2169 	if (parents_clbs[index] == NULL) {  in get_module_parent()
2174 	return parents_clbs[index](module);  in get_module_parent()