148 	uint8_t pin;  member
351 					      unsigned int pin);
360 	unsigned int shift_1b = gpio->pin;  in stm32_gpio_configure()
361 	unsigned int shift_2b = SHIFT_U32(gpio->pin, 1);  in stm32_gpio_configure()
408 		    state->gpio_pinctrl.pin == gpio->pin) {  in stm32_gpio_put_gpio()
412 			release_rif_semaphore_if_acquired(bank, gpio->pin);  in stm32_gpio_put_gpio()
449 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin)  in pin_is_accessible()  argument
460 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in pin_is_accessible()
480 						  unsigned int pin)  in acquire_rif_semaphore_if_needed()  argument
492 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in acquire_rif_semaphore_if_needed()
495 		res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin),  in acquire_rif_semaphore_if_needed()
504 				      unsigned int pin)  in semaphore_current_cid()  argument
506 	return (io_read32(bank->base + GPIO_SEMCR(pin)) >>  in semaphore_current_cid()
512 					      unsigned int pin)  in release_rif_semaphore_if_acquired()  argument
524 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in release_rif_semaphore_if_acquired()
527 	    semaphore_current_cid(bank, pin) == RIF_CID1) {  in release_rif_semaphore_if_acquired()
528 		res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin),  in release_rif_semaphore_if_acquired()
532 			     bank->bank_id + 'A', pin);  in release_rif_semaphore_if_acquired()
541 			      unsigned int pin __unused)  in pin_is_accessible()
548 				unsigned int pin __unused)  in acquire_rif_semaphore_if_needed()
555 				  unsigned int pin __unused)  in release_rif_semaphore_if_acquired()
560 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin)  in pin_is_secure()  argument
568 		secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin);  in pin_is_secure()
577 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg)  in get_gpio_cfg()  argument
591 	cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) &  in get_gpio_cfg()
594 	cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1;  in get_gpio_cfg()
597 		       (pin << 1)) & GPIO_OSPEED_MASK;  in get_gpio_cfg()
599 	cfg->pupd = (io_read32(bank->base +  GPIO_PUPDR_OFFSET) >> (pin << 1)) &  in get_gpio_cfg()
602 	cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;  in get_gpio_cfg()
604 	if (pin < GPIO_ALT_LOWER_LIMIT)  in get_gpio_cfg()
606 			   (pin << 2)) & GPIO_ALTERNATE_MASK;  in get_gpio_cfg()
609 			   ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) &  in get_gpio_cfg()
616 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg)  in set_gpio_cfg()  argument
627 			SHIFT_U32(GPIO_MODE_MASK, pin << 1),  in set_gpio_cfg()
628 			SHIFT_U32(cfg->mode, pin << 1));  in set_gpio_cfg()
631 	io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin),  in set_gpio_cfg()
632 			SHIFT_U32(cfg->otype, pin));  in set_gpio_cfg()
636 			SHIFT_U32(GPIO_OSPEED_MASK, pin << 1),  in set_gpio_cfg()
637 			SHIFT_U32(cfg->ospeed, pin << 1));  in set_gpio_cfg()
640 	io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin),  in set_gpio_cfg()
641 			SHIFT_U32(cfg->pupd, pin << 1));  in set_gpio_cfg()
644 	if (pin < GPIO_ALT_LOWER_LIMIT) {  in set_gpio_cfg()
646 				SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2),  in set_gpio_cfg()
647 				SHIFT_U32(cfg->af, pin << 2));  in set_gpio_cfg()
649 		size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2;  in set_gpio_cfg()
657 	io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin);  in set_gpio_cfg()
694 		uint32_t pin = 0;  in get_pinctrl_from_fdt()  local
706 		pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT;  in get_pinctrl_from_fdt()
762 			ref->pin = (uint8_t)pin;  in get_pinctrl_from_fdt()
776 			if (pin >= bank_ref->ngpios) {  in get_pinctrl_from_fdt()
779 				     bank + 'A', pin);  in get_pinctrl_from_fdt()
799 	unsigned int pin = handle->gpio_pinctrl.pin;  in consumed_gpios_pm()  local
803 		set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg);  in consumed_gpios_pm()
805 			stm32_gpio_set_level(chip, pin, handle->level);  in consumed_gpios_pm()
807 		get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg);  in consumed_gpios_pm()
809 			handle->level = stm32_gpio_get_level(chip, pin);  in consumed_gpios_pm()
834 	if (gpio->pin >= bank->ngpios) {  in stm32_gpio_get_dt()
851 		    reg_state->gpio_pinctrl.pin == gpio->pin) {  in stm32_gpio_get_dt()
853 			     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
860 	if (!pin_is_accessible(bank, gpio->pin)) {  in stm32_gpio_get_dt()
862 		     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
866 	res = acquire_rif_semaphore_if_needed(bank, gpio->pin);  in stm32_gpio_get_dt()
869 		     bank->bank_id + 'A', gpio->pin, consumer_name);  in stm32_gpio_get_dt()
875 		     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
879 	if (gpio_secure != pin_is_secure(bank, gpio->pin)) {  in stm32_gpio_get_dt()
882 		     bank->bank_id + 'A', gpio->pin,  in stm32_gpio_get_dt()
883 		     pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure",  in stm32_gpio_get_dt()
889 	state->gpio_pinctrl.pin = gpio->pin;  in stm32_gpio_get_dt()
1384 		if (!pin_is_accessible(bank, p[n].pin)) {  in stm32_pinctrl_conf_apply()
1386 			     p[n].bank + 'A', p[n].pin);  in stm32_pinctrl_conf_apply()
1391 		res = acquire_rif_semaphore_if_needed(bank, p[n].pin);  in stm32_pinctrl_conf_apply()
1394 			     bank->bank_id + 'A', p[n].pin);  in stm32_pinctrl_conf_apply()
1399 		if (p[n].cfg.nsec == !pin_is_secure(bank, p[n].pin))  in stm32_pinctrl_conf_apply()
1405 			     p[n].bank + 'A', p[n].pin,  in stm32_pinctrl_conf_apply()
1406 			     pin_is_secure(bank, p[n].pin) ? "" : "non-");  in stm32_pinctrl_conf_apply()
1410 			     p[n].bank + 'A', p[n].pin,  in stm32_pinctrl_conf_apply()
1411 			     pin_is_secure(bank, p[n].pin) ? "" : "non-");  in stm32_pinctrl_conf_apply()
1419 			release_rif_semaphore_if_acquired(bank, p[n].pin);  in stm32_pinctrl_conf_apply()
1426 		set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg);  in stm32_pinctrl_conf_apply()
1444 				 unsigned int *bank, unsigned int *pin,  in stm32_gpio_pinctrl_bank_pin()  argument
1463 		if (bank || pin) {  in stm32_gpio_pinctrl_bank_pin()
1467 				if (pin && pin_count < *count)  in stm32_gpio_pinctrl_bank_pin()
1468 					pin[pin_count] = ref->pinctrl[n].pin;  in stm32_gpio_pinctrl_bank_pin()
1632 	unsigned int pin = 0;  in apply_sec_cfg()  local
1657 			for (pin = 0; pin < bank->ngpios; pin++)  in apply_sec_cfg()
1658 				release_rif_semaphore_if_acquired(bank, pin);  in apply_sec_cfg()