147 	uint8_t bank;  member
234 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_chip_bank_id()  local
236 	return bank->bank_id;  in stm32_gpio_chip_bank_id()
242 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_get_level()  local
247 	assert(gpio_pin < bank->ngpios);  in stm32_gpio_get_level()
249 	if (clk_enable(bank->clock))  in stm32_gpio_get_level()
252 	mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) &  in stm32_gpio_get_level()
266 	if (io_read32(bank->base + reg_offset) & BIT(gpio_pin))  in stm32_gpio_get_level()
271 	clk_disable(bank->clock);  in stm32_gpio_get_level()
279 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_set_level()  local
281 	assert(gpio_pin < bank->ngpios);  in stm32_gpio_set_level()
283 	if (clk_enable(bank->clock))  in stm32_gpio_set_level()
287 		io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin));  in stm32_gpio_set_level()
289 		io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16));  in stm32_gpio_set_level()
291 	clk_disable(bank->clock);  in stm32_gpio_set_level()
297 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_get_direction()  local
300 	assert(gpio_pin < bank->ngpios);  in stm32_gpio_get_direction()
302 	if (clk_enable(bank->clock))  in stm32_gpio_get_direction()
305 	mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) &  in stm32_gpio_get_direction()
308 	clk_disable(bank->clock);  in stm32_gpio_get_direction()
324 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_set_direction()  local
328 	assert(gpio_pin < bank->ngpios);  in stm32_gpio_set_direction()
335 	if (clk_enable(bank->clock))  in stm32_gpio_set_direction()
338 	io_clrsetbits32(bank->base + GPIO_MODER_OFFSET,  in stm32_gpio_set_direction()
342 	clk_disable(bank->clock);  in stm32_gpio_set_direction()
350 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank,
356 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_configure()  local
377 	if (clk_enable(bank->clock))  in stm32_gpio_configure()
381 	io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET,  in stm32_gpio_configure()
385 	io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET,  in stm32_gpio_configure()
390 	clk_disable(bank->clock);  in stm32_gpio_configure()
397 	struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip);  in stm32_gpio_put_gpio()  local
407 		if (state->gpio_pinctrl.bank == bank->bank_id &&  in stm32_gpio_put_gpio()
412 			release_rif_semaphore_if_acquired(bank, gpio->pin);  in stm32_gpio_put_gpio()
439 	struct stm32_gpio_bank *bank = NULL;  in stm32_gpio_get_bank()  local
441 	STAILQ_FOREACH(bank, &bank_list, link)  in stm32_gpio_get_bank()
442 		if (bank_id == bank->bank_id)  in stm32_gpio_get_bank()
443 			return bank;  in stm32_gpio_get_bank()
449 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin)  in pin_is_accessible()  argument
454 	if (!bank->rif_cfg)  in pin_is_accessible()
457 	if (clk_enable(bank->clock))  in pin_is_accessible()
460 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in pin_is_accessible()
474 	clk_disable(bank->clock);  in pin_is_accessible()
479 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank,  in acquire_rif_semaphore_if_needed()  argument
485 	if (!bank->rif_cfg)  in acquire_rif_semaphore_if_needed()
488 	res = clk_enable(bank->clock);  in acquire_rif_semaphore_if_needed()
492 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in acquire_rif_semaphore_if_needed()
495 		res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin),  in acquire_rif_semaphore_if_needed()
498 	clk_disable(bank->clock);  in acquire_rif_semaphore_if_needed()
503 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank,  in semaphore_current_cid()  argument
506 	return (io_read32(bank->base + GPIO_SEMCR(pin)) >>  in semaphore_current_cid()
511 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank,  in release_rif_semaphore_if_acquired()  argument
517 	if (!bank->rif_cfg)  in release_rif_semaphore_if_acquired()
520 	res = clk_enable(bank->clock);  in release_rif_semaphore_if_acquired()
524 	cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin));  in release_rif_semaphore_if_acquired()
527 	    semaphore_current_cid(bank, pin) == RIF_CID1) {  in release_rif_semaphore_if_acquired()
528 		res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin),  in release_rif_semaphore_if_acquired()
532 			     bank->bank_id + 'A', pin);  in release_rif_semaphore_if_acquired()
537 	clk_disable(bank->clock);  in release_rif_semaphore_if_acquired()
540 static bool pin_is_accessible(struct stm32_gpio_bank *bank __unused,  in pin_is_accessible()
547 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused,  in acquire_rif_semaphore_if_needed()
554 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused,  in release_rif_semaphore_if_acquired()
560 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin)  in pin_is_secure()  argument
564 	if (bank->rif_cfg || bank->sec_support) {  in pin_is_secure()
565 		if (clk_enable(bank->clock))  in pin_is_secure()
568 		secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin);  in pin_is_secure()
570 		clk_disable(bank->clock);  in pin_is_secure()
579 	struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id);  in get_gpio_cfg()  local
581 	if (clk_enable(bank->clock))  in get_gpio_cfg()
591 	cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) &  in get_gpio_cfg()
594 	cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1;  in get_gpio_cfg()
596 	cfg->ospeed = (io_read32(bank->base +  GPIO_OSPEEDR_OFFSET) >>  in get_gpio_cfg()
599 	cfg->pupd = (io_read32(bank->base +  GPIO_PUPDR_OFFSET) >> (pin << 1)) &  in get_gpio_cfg()
602 	cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1;  in get_gpio_cfg()
605 		cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >>  in get_gpio_cfg()
608 		cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >>  in get_gpio_cfg()
612 	clk_disable(bank->clock);  in get_gpio_cfg()
618 	struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id);  in set_gpio_cfg()  local
621 	if (clk_enable(bank->clock))  in set_gpio_cfg()
626 	io_clrsetbits32(bank->base + GPIO_MODER_OFFSET,  in set_gpio_cfg()
631 	io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin),  in set_gpio_cfg()
635 	io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET,  in set_gpio_cfg()
640 	io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin),  in set_gpio_cfg()
645 		io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET,  in set_gpio_cfg()
651 		io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET,  in set_gpio_cfg()
657 	io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin);  in set_gpio_cfg()
660 	clk_disable(bank->clock);  in set_gpio_cfg()
693 		uint32_t bank = 0;  in get_pinctrl_from_fdt()  local
704 		bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT;  in get_pinctrl_from_fdt()
761 			ref->bank = (uint8_t)bank;  in get_pinctrl_from_fdt()
774 			bank_ref = stm32_gpio_get_bank(bank);  in get_pinctrl_from_fdt()
779 				     bank + 'A', pin);  in get_pinctrl_from_fdt()
798 	unsigned int bank_id = handle->gpio_pinctrl.bank;  in consumed_gpios_pm()
823 	struct stm32_gpio_bank *bank = data;  in stm32_gpio_get_dt()  local
834 	if (gpio->pin >= bank->ngpios) {  in stm32_gpio_get_dt()
850 		if (reg_state->gpio_pinctrl.bank == bank->bank_id &&  in stm32_gpio_get_dt()
853 			     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
860 	if (!pin_is_accessible(bank, gpio->pin)) {  in stm32_gpio_get_dt()
862 		     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
866 	res = acquire_rif_semaphore_if_needed(bank, gpio->pin);  in stm32_gpio_get_dt()
869 		     bank->bank_id + 'A', gpio->pin, consumer_name);  in stm32_gpio_get_dt()
873 	if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) {  in stm32_gpio_get_dt()
875 		     consumer_name, bank->bank_id + 'A', gpio->pin);  in stm32_gpio_get_dt()
879 	if (gpio_secure != pin_is_secure(bank, gpio->pin)) {  in stm32_gpio_get_dt()
882 		     bank->bank_id + 'A', gpio->pin,  in stm32_gpio_get_dt()
883 		     pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure",  in stm32_gpio_get_dt()
890 	state->gpio_pinctrl.bank = bank->bank_id;  in stm32_gpio_get_dt()
895 	gpio->chip = &bank->gpio_chip;  in stm32_gpio_get_dt()
928 	struct stm32_gpio_bank *bank = NULL;  in bank_is_registered()  local
930 	STAILQ_FOREACH(bank, &bank_list, link)  in bank_is_registered()
931 		if (bank->bank_id == bank_id)  in bank_is_registered()
938 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank,  in handle_available_semaphores()  argument
945 	for (i = 0 ; i < bank->ngpios; i++) {  in handle_available_semaphores()
949 		cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i));  in handle_available_semaphores()
954 		if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) {  in handle_available_semaphores()
955 			res = stm32_rif_release_semaphore(bank->base +  in handle_available_semaphores()
964 			res = stm32_rif_acquire_semaphore(bank->base +  in handle_available_semaphores()
978 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank,  in apply_rif_config()  argument
984 	if (!bank->rif_cfg)  in apply_rif_config()
987 	if (clk_enable(bank->clock))  in apply_rif_config()
990 	if (bank->is_tdcid) {  in apply_rif_config()
991 		for (i = 0; i < bank->ngpios; i++) {  in apply_rif_config()
1001 			io_clrbits32(bank->base + GPIO_CIDCFGR(i),  in apply_rif_config()
1005 		res = handle_available_semaphores(bank, gpios_mask);  in apply_rif_config()
1011 	io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET,  in apply_rif_config()
1012 		  bank->rif_cfg->priv_conf[0], gpios_mask);  in apply_rif_config()
1013 	io_mask32(bank->base + GPIO_SECR_OFFSET,  in apply_rif_config()
1014 		  bank->rif_cfg->sec_conf[0], gpios_mask);  in apply_rif_config()
1016 	if (!bank->is_tdcid) {  in apply_rif_config()
1021 	for (i = 0; i < bank->ngpios; i++) {  in apply_rif_config()
1025 		io_clrsetbits32(bank->base + GPIO_CIDCFGR(i),  in apply_rif_config()
1027 				bank->rif_cfg->cid_confs[i]);  in apply_rif_config()
1034 	io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET,  in apply_rif_config()
1035 		     bank->rif_cfg->lock_conf[0]);  in apply_rif_config()
1037 	res = handle_available_semaphores(bank, gpios_mask);  in apply_rif_config()
1044 		if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) &  in apply_rif_config()
1046 		    (bank->rif_cfg->priv_conf[0] & gpios_mask)) {  in apply_rif_config()
1048 			     'A' + bank->bank_id);  in apply_rif_config()
1052 		if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) !=  in apply_rif_config()
1053 		    (bank->rif_cfg->sec_conf[0] & gpios_mask)) {  in apply_rif_config()
1055 			     'A' + bank->bank_id);  in apply_rif_config()
1060 	clk_disable(bank->clock);  in apply_rif_config()
1065 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused,  in apply_rif_config()
1073 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank);
1077 	struct stm32_gpio_bank *bank = firewall->ctrl->priv;  in stm32_gpio_fw_configure()  local
1082 	assert(bank->sec_support);  in stm32_gpio_fw_configure()
1089 	if (bank->rif_cfg) {  in stm32_gpio_fw_configure()
1093 		bank->rif_cfg->access_mask[0] |= gpios_mask;  in stm32_gpio_fw_configure()
1099 		stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg,  in stm32_gpio_fw_configure()
1100 				    bank->ngpios);  in stm32_gpio_fw_configure()
1101 		return apply_rif_config(bank, gpios_mask);  in stm32_gpio_fw_configure()
1114 	if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) {  in stm32_gpio_fw_configure()
1116 		     gpios_mask, 'A' + bank->bank_id);  in stm32_gpio_fw_configure()
1122 		bank->seccfgr |= gpios_mask;  in stm32_gpio_fw_configure()
1124 		bank->seccfgr &= ~gpios_mask;  in stm32_gpio_fw_configure()
1126 	stm32_gpio_set_conf_sec(bank);  in stm32_gpio_fw_configure()
1135 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank)  in stm32_gpio_save_rif_config()  argument
1139 	for (i = 0; i < bank->ngpios; i++)  in stm32_gpio_save_rif_config()
1140 		bank->rif_cfg->cid_confs[i] = io_read32(bank->base +  in stm32_gpio_save_rif_config()
1143 	bank->rif_cfg->priv_conf[0] = io_read32(bank->base +  in stm32_gpio_save_rif_config()
1145 	bank->rif_cfg->sec_conf[0] = io_read32(bank->base +  in stm32_gpio_save_rif_config()
1147 	bank->rif_cfg->lock_conf[0] = io_read32(bank->base +  in stm32_gpio_save_rif_config()
1151 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank,  in stm32_parse_gpio_rif_conf()  argument
1165 	bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg));  in stm32_parse_gpio_rif_conf()
1166 	if (!bank->rif_cfg)  in stm32_parse_gpio_rif_conf()
1169 	bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t));  in stm32_parse_gpio_rif_conf()
1170 	if (!bank->rif_cfg->sec_conf)  in stm32_parse_gpio_rif_conf()
1174 			  bank->ngpios);  in stm32_parse_gpio_rif_conf()
1176 	bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t));  in stm32_parse_gpio_rif_conf()
1177 	bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t));  in stm32_parse_gpio_rif_conf()
1178 	bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t));  in stm32_parse_gpio_rif_conf()
1179 	bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t));  in stm32_parse_gpio_rif_conf()
1180 	if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask ||  in stm32_parse_gpio_rif_conf()
1181 	    !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf)  in stm32_parse_gpio_rif_conf()
1185 		stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg,  in stm32_parse_gpio_rif_conf()
1186 				    bank->ngpios);  in stm32_parse_gpio_rif_conf()
1197 	struct stm32_gpio_bank *bank = NULL;  in dt_stm32_gpio_bank()  local
1213 	bank = calloc(1, sizeof(*bank));  in dt_stm32_gpio_bank()
1214 	if (!bank)  in dt_stm32_gpio_bank()
1218 		res = stm32_rifsc_check_tdcid(&bank->is_tdcid);  in dt_stm32_gpio_bank()
1220 			free(bank);  in dt_stm32_gpio_bank()
1235 	bank->bank_id = dt_get_bank_id(fdt, node);  in dt_stm32_gpio_bank()
1236 	bank->clock = clk;  in dt_stm32_gpio_bank()
1237 	bank->gpio_chip.ops = &stm32_gpio_ops;  in dt_stm32_gpio_bank()
1238 	bank->sec_support = compat->secure_control;  in dt_stm32_gpio_bank()
1248 		bank->ngpios = MAX(bank->ngpios,  in dt_stm32_gpio_bank()
1256 		bank->base = io_pa_or_va_secure(&pa_va, blen);  in dt_stm32_gpio_bank()
1258 		stm32_parse_gpio_rif_conf(bank, fdt, node);  in dt_stm32_gpio_bank()
1259 	} else if (bank->sec_support) {  in dt_stm32_gpio_bank()
1261 		bank->base = io_pa_or_va_secure(&pa_va, blen);  in dt_stm32_gpio_bank()
1264 			bank->seccfgr = fdt32_to_cpu(*cuint);  in dt_stm32_gpio_bank()
1267 			     bank->bank_id + 'A');  in dt_stm32_gpio_bank()
1269 		bank->base = io_pa_or_va_nsec(&pa_va, blen);  in dt_stm32_gpio_bank()
1272 	*out_bank = bank;  in dt_stm32_gpio_bank()
1278 					       struct stm32_gpio_bank *bank)  in stm32_gpio_firewall_register()  argument
1286 	    !bank->sec_support)  in stm32_gpio_firewall_register()
1293 	bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id;  in stm32_gpio_firewall_register()
1297 	controller->priv = bank;  in stm32_gpio_firewall_register()
1339 			struct stm32_gpio_bank *bank = NULL;  in dt_stm32_gpio_pinctrl()  local
1346 						 range_offs, &bank);  in dt_stm32_gpio_pinctrl()
1352 						     stm32_gpio_get_dt, bank);  in dt_stm32_gpio_pinctrl()
1356 			res = stm32_gpio_firewall_register(fdt, b_node, bank);  in dt_stm32_gpio_pinctrl()
1360 			STAILQ_INSERT_TAIL(&bank_list, bank, link);  in dt_stm32_gpio_pinctrl()
1375 	struct stm32_gpio_bank *bank = NULL;  in stm32_pinctrl_conf_apply()  local
1382 		bank = stm32_gpio_get_bank(p[n].bank);  in stm32_pinctrl_conf_apply()
1384 		if (!pin_is_accessible(bank, p[n].pin)) {  in stm32_pinctrl_conf_apply()
1386 			     p[n].bank + 'A', p[n].pin);  in stm32_pinctrl_conf_apply()
1391 		res = acquire_rif_semaphore_if_needed(bank, p[n].pin);  in stm32_pinctrl_conf_apply()
1394 			     bank->bank_id + 'A', p[n].pin);  in stm32_pinctrl_conf_apply()
1399 		if (p[n].cfg.nsec == !pin_is_secure(bank, p[n].pin))  in stm32_pinctrl_conf_apply()
1405 			     p[n].bank + 'A', p[n].pin,  in stm32_pinctrl_conf_apply()
1406 			     pin_is_secure(bank, p[n].pin) ? "" : "non-");  in stm32_pinctrl_conf_apply()
1410 			     p[n].bank + 'A', p[n].pin,  in stm32_pinctrl_conf_apply()
1411 			     pin_is_secure(bank, p[n].pin) ? "" : "non-");  in stm32_pinctrl_conf_apply()
1418 			bank = stm32_gpio_get_bank(p[n].bank);  in stm32_pinctrl_conf_apply()
1419 			release_rif_semaphore_if_acquired(bank, p[n].pin);  in stm32_pinctrl_conf_apply()
1426 		set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg);  in stm32_pinctrl_conf_apply()
1444 				 unsigned int *bank, unsigned int *pin,  in stm32_gpio_pinctrl_bank_pin()  argument
1463 		if (bank || pin) {  in stm32_gpio_pinctrl_bank_pin()
1465 				if (bank && pin_count < *count)  in stm32_gpio_pinctrl_bank_pin()
1466 					bank[pin_count] = ref->pinctrl[n].bank;  in stm32_gpio_pinctrl_bank_pin()
1541 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank)  in stm32_gpio_get_conf_sec()  argument
1543 	if (bank->sec_support) {  in stm32_gpio_get_conf_sec()
1544 		clk_enable(bank->clock);  in stm32_gpio_get_conf_sec()
1545 		bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET);  in stm32_gpio_get_conf_sec()
1546 		clk_disable(bank->clock);  in stm32_gpio_get_conf_sec()
1550 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank)  in stm32_gpio_set_conf_sec()  argument
1552 	if (bank->sec_support) {  in stm32_gpio_set_conf_sec()
1553 		clk_enable(bank->clock);  in stm32_gpio_set_conf_sec()
1554 		io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr);  in stm32_gpio_set_conf_sec()
1555 		clk_disable(bank->clock);  in stm32_gpio_set_conf_sec()
1562 	struct stm32_gpio_bank *bank = NULL;  in stm32_gpio_sec_config_resume()  local
1564 	STAILQ_FOREACH(bank, &bank_list, link) {  in stm32_gpio_sec_config_resume()
1565 		if (bank->rif_cfg) {  in stm32_gpio_sec_config_resume()
1566 			if (!bank->is_tdcid)  in stm32_gpio_sec_config_resume()
1569 			bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios,  in stm32_gpio_sec_config_resume()
1572 			res = apply_rif_config(bank,  in stm32_gpio_sec_config_resume()
1573 					       bank->rif_cfg->access_mask[0]);  in stm32_gpio_sec_config_resume()
1576 				     'A' + bank->bank_id);  in stm32_gpio_sec_config_resume()
1580 			stm32_gpio_set_conf_sec(bank);  in stm32_gpio_sec_config_resume()
1589 	struct stm32_gpio_bank *bank = NULL;  in stm32_gpio_sec_config_suspend()  local
1591 	STAILQ_FOREACH(bank, &bank_list, link) {  in stm32_gpio_sec_config_suspend()
1592 		if (bank->rif_cfg) {  in stm32_gpio_sec_config_suspend()
1593 			if (bank->is_tdcid)  in stm32_gpio_sec_config_suspend()
1594 				stm32_gpio_save_rif_config(bank);  in stm32_gpio_sec_config_suspend()
1596 			stm32_gpio_get_conf_sec(bank);  in stm32_gpio_sec_config_suspend()
1631 	struct stm32_gpio_bank *bank = NULL;  in apply_sec_cfg()  local
1634 	STAILQ_FOREACH(bank, &bank_list, link) {  in apply_sec_cfg()
1635 		if (bank->ready)  in apply_sec_cfg()
1638 		if (bank->rif_cfg) {  in apply_sec_cfg()
1639 			res = apply_rif_config(bank,  in apply_sec_cfg()
1640 					       bank->rif_cfg->access_mask[0]);  in apply_sec_cfg()
1643 				     'A' + bank->bank_id);  in apply_sec_cfg()
1644 				STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank,  in apply_sec_cfg()
1646 				free(bank);  in apply_sec_cfg()
1657 			for (pin = 0; pin < bank->ngpios; pin++)  in apply_sec_cfg()
1658 				release_rif_semaphore_if_acquired(bank, pin);  in apply_sec_cfg()
1661 			stm32_gpio_set_conf_sec(bank);  in apply_sec_cfg()
1664 		bank->ready = true;  in apply_sec_cfg()