Lines Matching +full:runs +full:- +full:on
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2024, STMicroelectronics
17 #include <dt-bindings/gpio/stm32mp_gpio.h>
18 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
127 * @nsec: Hint on expected secure state of the pin: 0 if secure, 1 otherwise
153 * struct stm32_pinctrl_array - Array of pins in a pin control state
163 * struct stm32_gpio_bank - GPIO bank instance
172 * @seccfgr: non-RIF bank secure configuration data
175 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID
194 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose
236 return bank->bank_id; in stm32_gpio_chip_bank_id()
247 assert(gpio_pin < bank->ngpios); in stm32_gpio_get_level()
249 if (clk_enable(bank->clock)) in stm32_gpio_get_level()
252 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & in stm32_gpio_get_level()
266 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) in stm32_gpio_get_level()
271 clk_disable(bank->clock); in stm32_gpio_get_level()
281 assert(gpio_pin < bank->ngpios); in stm32_gpio_set_level()
283 if (clk_enable(bank->clock)) in stm32_gpio_set_level()
287 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); in stm32_gpio_set_level()
289 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); in stm32_gpio_set_level()
291 clk_disable(bank->clock); in stm32_gpio_set_level()
300 assert(gpio_pin < bank->ngpios); in stm32_gpio_get_direction()
302 if (clk_enable(bank->clock)) in stm32_gpio_get_direction()
305 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & in stm32_gpio_get_direction()
308 clk_disable(bank->clock); in stm32_gpio_get_direction()
328 assert(gpio_pin < bank->ngpios); in stm32_gpio_set_direction()
335 if (clk_enable(bank->clock)) in stm32_gpio_set_direction()
338 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, in stm32_gpio_set_direction()
342 clk_disable(bank->clock); in stm32_gpio_set_direction()
360 unsigned int shift_1b = gpio->pin; in stm32_gpio_configure()
361 unsigned int shift_2b = SHIFT_U32(gpio->pin, 1); in stm32_gpio_configure()
365 if (gpio->dt_flags & GPIO_PULL_UP) in stm32_gpio_configure()
367 else if (gpio->dt_flags & GPIO_PULL_DOWN) in stm32_gpio_configure()
372 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) in stm32_gpio_configure()
377 if (clk_enable(bank->clock)) in stm32_gpio_configure()
381 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, in stm32_gpio_configure()
385 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, in stm32_gpio_configure()
390 clk_disable(bank->clock); in stm32_gpio_configure()
407 if (state->gpio_pinctrl.bank == bank->bank_id && in stm32_gpio_put_gpio()
408 state->gpio_pinctrl.pin == gpio->pin) { in stm32_gpio_put_gpio()
412 release_rif_semaphore_if_acquired(bank, gpio->pin); in stm32_gpio_put_gpio()
434 return chip && chip->ops == &stm32_gpio_ops; in is_stm32_gpio_chip()
442 if (bank_id == bank->bank_id) in stm32_gpio_get_bank()
454 if (!bank->rif_cfg) in pin_is_accessible()
457 if (clk_enable(bank->clock)) in pin_is_accessible()
460 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in pin_is_accessible()
474 clk_disable(bank->clock); in pin_is_accessible()
485 if (!bank->rif_cfg) in acquire_rif_semaphore_if_needed()
488 res = clk_enable(bank->clock); in acquire_rif_semaphore_if_needed()
492 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in acquire_rif_semaphore_if_needed()
495 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin), in acquire_rif_semaphore_if_needed()
498 clk_disable(bank->clock); in acquire_rif_semaphore_if_needed()
506 return (io_read32(bank->base + GPIO_SEMCR(pin)) >> in semaphore_current_cid()
508 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0); in semaphore_current_cid()
517 if (!bank->rif_cfg) in release_rif_semaphore_if_acquired()
520 res = clk_enable(bank->clock); in release_rif_semaphore_if_acquired()
524 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); in release_rif_semaphore_if_acquired()
528 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin), in release_rif_semaphore_if_acquired()
532 bank->bank_id + 'A', pin); in release_rif_semaphore_if_acquired()
537 clk_disable(bank->clock); in release_rif_semaphore_if_acquired()
564 if (bank->rif_cfg || bank->sec_support) { in pin_is_secure()
565 if (clk_enable(bank->clock)) in pin_is_secure()
568 secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin); in pin_is_secure()
570 clk_disable(bank->clock); in pin_is_secure()
581 if (clk_enable(bank->clock)) in get_gpio_cfg()
591 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
594 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; in get_gpio_cfg()
596 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> in get_gpio_cfg()
599 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
602 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; in get_gpio_cfg()
605 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> in get_gpio_cfg()
608 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> in get_gpio_cfg()
609 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & in get_gpio_cfg()
612 clk_disable(bank->clock); in get_gpio_cfg()
621 if (clk_enable(bank->clock)) in set_gpio_cfg()
626 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, in set_gpio_cfg()
628 SHIFT_U32(cfg->mode, pin << 1)); in set_gpio_cfg()
631 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), in set_gpio_cfg()
632 SHIFT_U32(cfg->otype, pin)); in set_gpio_cfg()
635 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, in set_gpio_cfg()
637 SHIFT_U32(cfg->ospeed, pin << 1)); in set_gpio_cfg()
640 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), in set_gpio_cfg()
641 SHIFT_U32(cfg->pupd, pin << 1)); in set_gpio_cfg()
645 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, in set_gpio_cfg()
647 SHIFT_U32(cfg->af, pin << 2)); in set_gpio_cfg()
649 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; in set_gpio_cfg()
651 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, in set_gpio_cfg()
653 SHIFT_U32(cfg->af, shift)); in set_gpio_cfg()
657 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); in set_gpio_cfg()
660 clk_disable(bank->clock); in set_gpio_cfg()
680 return -FDT_ERR_NOTFOUND; in get_pinctrl_from_fdt()
682 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); in get_pinctrl_from_fdt()
686 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) in get_pinctrl_from_fdt()
688 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) in get_pinctrl_from_fdt()
732 alternate = mode - 1U; in get_pinctrl_from_fdt()
743 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) in get_pinctrl_from_fdt()
746 if (fdt_getprop(fdt, node, "output-high", NULL) && in get_pinctrl_from_fdt()
752 if (fdt_getprop(fdt, node, "output-low", NULL) && in get_pinctrl_from_fdt()
761 ref->bank = (uint8_t)bank; in get_pinctrl_from_fdt()
762 ref->pin = (uint8_t)pin; in get_pinctrl_from_fdt()
763 ref->cfg.mode = mode; in get_pinctrl_from_fdt()
765 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; in get_pinctrl_from_fdt()
767 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; in get_pinctrl_from_fdt()
768 ref->cfg.ospeed = speed; in get_pinctrl_from_fdt()
769 ref->cfg.pupd = pull; in get_pinctrl_from_fdt()
770 ref->cfg.od = odata; in get_pinctrl_from_fdt()
771 ref->cfg.af = alternate; in get_pinctrl_from_fdt()
772 ref->cfg.nsec = pin_non_secure; in get_pinctrl_from_fdt()
776 if (pin >= bank_ref->ngpios) { in get_pinctrl_from_fdt()
797 struct stm32_gpio_pm_state *handle = pm_hdl->handle; in consumed_gpios_pm()
798 unsigned int bank_id = handle->gpio_pinctrl.bank; in consumed_gpios_pm()
799 unsigned int pin = handle->gpio_pinctrl.pin; in consumed_gpios_pm()
800 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; in consumed_gpios_pm()
803 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); in consumed_gpios_pm()
804 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) in consumed_gpios_pm()
805 stm32_gpio_set_level(chip, pin, handle->level); in consumed_gpios_pm()
807 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); in consumed_gpios_pm()
808 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) in consumed_gpios_pm()
809 handle->level = stm32_gpio_get_level(chip, pin); in consumed_gpios_pm()
827 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node, in stm32_gpio_get_dt()
834 if (gpio->pin >= bank->ngpios) { in stm32_gpio_get_dt()
840 if (gpio->dt_flags & GPIO_STM32_NSEC) in stm32_gpio_get_dt()
850 if (reg_state->gpio_pinctrl.bank == bank->bank_id && in stm32_gpio_get_dt()
851 reg_state->gpio_pinctrl.pin == gpio->pin) { in stm32_gpio_get_dt()
853 consumer_name, bank->bank_id + 'A', gpio->pin); in stm32_gpio_get_dt()
860 if (!pin_is_accessible(bank, gpio->pin)) { in stm32_gpio_get_dt()
861 EMSG("node %s requests pin on GPIO %c%u which access is denied", in stm32_gpio_get_dt()
862 consumer_name, bank->bank_id + 'A', gpio->pin); in stm32_gpio_get_dt()
866 res = acquire_rif_semaphore_if_needed(bank, gpio->pin); in stm32_gpio_get_dt()
869 bank->bank_id + 'A', gpio->pin, consumer_name); in stm32_gpio_get_dt()
873 if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) { in stm32_gpio_get_dt()
875 consumer_name, bank->bank_id + 'A', gpio->pin); in stm32_gpio_get_dt()
879 if (gpio_secure != pin_is_secure(bank, gpio->pin)) { in stm32_gpio_get_dt()
881 consumer_name, gpio_secure ? "secure" : "non-secure", in stm32_gpio_get_dt()
882 bank->bank_id + 'A', gpio->pin, in stm32_gpio_get_dt()
883 pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure", in stm32_gpio_get_dt()
884 fdt_get_name(pargs->fdt, pargs->phandle_node, NULL)); in stm32_gpio_get_dt()
889 state->gpio_pinctrl.pin = gpio->pin; in stm32_gpio_get_dt()
890 state->gpio_pinctrl.bank = bank->bank_id; in stm32_gpio_get_dt()
893 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); in stm32_gpio_get_dt()
895 gpio->chip = &bank->gpio_chip; in stm32_gpio_get_dt()
902 /* Get bank ID from bank node property st,bank-name or panic on failure */
909 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ in dt_get_bank_id()
910 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); in dt_get_bank_id()
912 panic("Missing/wrong st,bank-name property"); in dt_get_bank_id()
914 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || in dt_get_bank_id()
916 panic("Wrong st,bank-name property"); in dt_get_bank_id()
931 if (bank->bank_id == bank_id) in bank_is_registered()
945 for (i = 0 ; i < bank->ngpios; i++) { in handle_available_semaphores()
949 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); in handle_available_semaphores()
954 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { in handle_available_semaphores()
955 res = stm32_rif_release_semaphore(bank->base + in handle_available_semaphores()
964 res = stm32_rif_acquire_semaphore(bank->base + in handle_available_semaphores()
984 if (!bank->rif_cfg) in apply_rif_config()
987 if (clk_enable(bank->clock)) in apply_rif_config()
990 if (bank->is_tdcid) { in apply_rif_config()
991 for (i = 0; i < bank->ngpios; i++) { in apply_rif_config()
996 * When TDCID, OP-TEE should be the one to set the CID in apply_rif_config()
1001 io_clrbits32(bank->base + GPIO_CIDCFGR(i), in apply_rif_config()
1011 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, in apply_rif_config()
1012 bank->rif_cfg->priv_conf[0], gpios_mask); in apply_rif_config()
1013 io_mask32(bank->base + GPIO_SECR_OFFSET, in apply_rif_config()
1014 bank->rif_cfg->sec_conf[0], gpios_mask); in apply_rif_config()
1016 if (!bank->is_tdcid) { in apply_rif_config()
1021 for (i = 0; i < bank->ngpios; i++) { in apply_rif_config()
1025 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), in apply_rif_config()
1027 bank->rif_cfg->cid_confs[i]); in apply_rif_config()
1034 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, in apply_rif_config()
1035 bank->rif_cfg->lock_conf[0]); in apply_rif_config()
1044 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & in apply_rif_config()
1046 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { in apply_rif_config()
1048 'A' + bank->bank_id); in apply_rif_config()
1052 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != in apply_rif_config()
1053 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { in apply_rif_config()
1055 'A' + bank->bank_id); in apply_rif_config()
1060 clk_disable(bank->clock); in apply_rif_config()
1077 struct stm32_gpio_bank *bank = firewall->ctrl->priv; in stm32_gpio_fw_configure()
1082 assert(bank->sec_support); in stm32_gpio_fw_configure()
1084 if (firewall->arg_count != 1) in stm32_gpio_fw_configure()
1087 firewall_arg = firewall->args[0]; in stm32_gpio_fw_configure()
1089 if (bank->rif_cfg) { in stm32_gpio_fw_configure()
1093 bank->rif_cfg->access_mask[0] |= gpios_mask; in stm32_gpio_fw_configure()
1099 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, in stm32_gpio_fw_configure()
1100 bank->ngpios); in stm32_gpio_fw_configure()
1108 * are non-secure (flag set) or non-secure (flag cleared). in stm32_gpio_fw_configure()
1114 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { in stm32_gpio_fw_configure()
1116 gpios_mask, 'A' + bank->bank_id); in stm32_gpio_fw_configure()
1122 bank->seccfgr |= gpios_mask; in stm32_gpio_fw_configure()
1124 bank->seccfgr &= ~gpios_mask; in stm32_gpio_fw_configure()
1139 for (i = 0; i < bank->ngpios; i++) in stm32_gpio_save_rif_config()
1140 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + in stm32_gpio_save_rif_config()
1143 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + in stm32_gpio_save_rif_config()
1145 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + in stm32_gpio_save_rif_config()
1147 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + in stm32_gpio_save_rif_config()
1165 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); in stm32_parse_gpio_rif_conf()
1166 if (!bank->rif_cfg) in stm32_parse_gpio_rif_conf()
1169 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); in stm32_parse_gpio_rif_conf()
1170 if (!bank->rif_cfg->sec_conf) in stm32_parse_gpio_rif_conf()
1174 bank->ngpios); in stm32_parse_gpio_rif_conf()
1176 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); in stm32_parse_gpio_rif_conf()
1177 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); in stm32_parse_gpio_rif_conf()
1178 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); in stm32_parse_gpio_rif_conf()
1179 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); in stm32_parse_gpio_rif_conf()
1180 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || in stm32_parse_gpio_rif_conf()
1181 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) in stm32_parse_gpio_rif_conf()
1185 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, in stm32_parse_gpio_rif_conf()
1186 bank->ngpios); in stm32_parse_gpio_rif_conf()
1217 if (compat->secure_extended) { in dt_stm32_gpio_bank()
1218 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); in dt_stm32_gpio_bank()
1226 * Do not rely *only* on the "reg" property to get the address, in dt_stm32_gpio_bank()
1235 bank->bank_id = dt_get_bank_id(fdt, node); in dt_stm32_gpio_bank()
1236 bank->clock = clk; in dt_stm32_gpio_bank()
1237 bank->gpio_chip.ops = &stm32_gpio_ops; in dt_stm32_gpio_bank()
1238 bank->sec_support = compat->secure_control; in dt_stm32_gpio_bank()
1240 /* Parse gpio-ranges with its 4 parameters */ in dt_stm32_gpio_bank()
1241 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); in dt_stm32_gpio_bank()
1244 panic("wrong gpio-ranges syntax"); in dt_stm32_gpio_bank()
1248 bank->ngpios = MAX(bank->ngpios, in dt_stm32_gpio_bank()
1254 if (compat->secure_extended) { in dt_stm32_gpio_bank()
1256 bank->base = io_pa_or_va_secure(&pa_va, blen); in dt_stm32_gpio_bank()
1259 } else if (bank->sec_support) { in dt_stm32_gpio_bank()
1261 bank->base = io_pa_or_va_secure(&pa_va, blen); in dt_stm32_gpio_bank()
1264 bank->seccfgr = fdt32_to_cpu(*cuint); in dt_stm32_gpio_bank()
1266 DMSG("GPIO bank %c assigned to non-secure", in dt_stm32_gpio_bank()
1267 bank->bank_id + 'A'); in dt_stm32_gpio_bank()
1269 bank->base = io_pa_or_va_nsec(&pa_va, blen); in dt_stm32_gpio_bank()
1282 char bank_name[] = "gpio-bank-X"; in stm32_gpio_firewall_register()
1286 !bank->sec_support) in stm32_gpio_firewall_register()
1293 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; in stm32_gpio_firewall_register()
1296 controller->name = name; in stm32_gpio_firewall_register()
1297 controller->priv = bank; in stm32_gpio_firewall_register()
1298 controller->ops = &stm32_gpio_firewall_ops; in stm32_gpio_firewall_register()
1300 if (!controller->name) in stm32_gpio_firewall_register()
1329 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); in dt_stm32_gpio_pinctrl()
1332 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); in dt_stm32_gpio_pinctrl()
1335 * We found a property "gpio-controller" in the node: in dt_stm32_gpio_pinctrl()
1362 if (len != -FDT_ERR_NOTFOUND) in dt_stm32_gpio_pinctrl()
1373 struct stm32_pinctrl_array *ref = conf->priv; in stm32_pinctrl_conf_apply()
1374 struct stm32_pinctrl *p = ref->pinctrl; in stm32_pinctrl_conf_apply()
1377 size_t pin_count = ref->count; in stm32_pinctrl_conf_apply()
1394 bank->bank_id + 'A', p[n].pin); in stm32_pinctrl_conf_apply()
1404 p[n].cfg.nsec ? "non-" : "", in stm32_pinctrl_conf_apply()
1406 pin_is_secure(bank, p[n].pin) ? "" : "non-"); in stm32_pinctrl_conf_apply()
1409 p[n].cfg.nsec ? "non-" : "", in stm32_pinctrl_conf_apply()
1411 pin_is_secure(bank, p[n].pin) ? "" : "non-"); in stm32_pinctrl_conf_apply()
1455 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { in stm32_gpio_pinctrl_bank_pin()
1456 struct pinconf *pinconf = pinctrl->confs[conf_index]; in stm32_gpio_pinctrl_bank_pin()
1457 struct stm32_pinctrl_array *ref = pinconf->priv; in stm32_gpio_pinctrl_bank_pin()
1460 if (pinconf->ops != &stm32_pinctrl_ops) in stm32_gpio_pinctrl_bank_pin()
1464 for (n = 0; n < ref->count; n++) { in stm32_gpio_pinctrl_bank_pin()
1466 bank[pin_count] = ref->pinctrl[n].bank; in stm32_gpio_pinctrl_bank_pin()
1468 pin[pin_count] = ref->pinctrl[n].pin; in stm32_gpio_pinctrl_bank_pin()
1472 pin_count += ref->count; in stm32_gpio_pinctrl_bank_pin()
1497 pinctrl_node = pargs->phandle_node; in stm32_pinctrl_dt_get()
1498 fdt = pargs->fdt; in stm32_pinctrl_dt_get()
1504 else if (count != -FDT_ERR_NOTFOUND) in stm32_pinctrl_dt_get()
1512 pinconf = &loc_conf->pinconf; in stm32_pinctrl_dt_get()
1513 pinconf->ops = &stm32_pinctrl_ops; in stm32_pinctrl_dt_get()
1514 pinconf->priv = &loc_conf->array_ref; in stm32_pinctrl_dt_get()
1516 loc_conf->array_ref.count = pin_count; in stm32_pinctrl_dt_get()
1517 pinctrl = loc_conf->array_ref.pinctrl; in stm32_pinctrl_dt_get()
1524 pargs->consumer_node, in stm32_pinctrl_dt_get()
1526 pin_count - count); in stm32_pinctrl_dt_get()
1527 if (found <= 0 && found > ((int)pin_count - count)) { in stm32_pinctrl_dt_get()
1543 if (bank->sec_support) { in stm32_gpio_get_conf_sec()
1544 clk_enable(bank->clock); in stm32_gpio_get_conf_sec()
1545 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); in stm32_gpio_get_conf_sec()
1546 clk_disable(bank->clock); in stm32_gpio_get_conf_sec()
1552 if (bank->sec_support) { in stm32_gpio_set_conf_sec()
1553 clk_enable(bank->clock); in stm32_gpio_set_conf_sec()
1554 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); in stm32_gpio_set_conf_sec()
1555 clk_disable(bank->clock); in stm32_gpio_set_conf_sec()
1565 if (bank->rif_cfg) { in stm32_gpio_sec_config_resume()
1566 if (!bank->is_tdcid) in stm32_gpio_sec_config_resume()
1569 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, in stm32_gpio_sec_config_resume()
1573 bank->rif_cfg->access_mask[0]); in stm32_gpio_sec_config_resume()
1576 'A' + bank->bank_id); in stm32_gpio_sec_config_resume()
1592 if (bank->rif_cfg) { in stm32_gpio_sec_config_suspend()
1593 if (bank->is_tdcid) in stm32_gpio_sec_config_suspend()
1635 if (bank->ready) in apply_sec_cfg()
1638 if (bank->rif_cfg) { in apply_sec_cfg()
1640 bank->rif_cfg->access_mask[0]); in apply_sec_cfg()
1643 'A' + bank->bank_id); in apply_sec_cfg()
1657 for (pin = 0; pin < bank->ngpios; pin++) in apply_sec_cfg()
1664 bank->ready = true; in apply_sec_cfg()
1692 "stm32-gpio-secure-config"); in stm32_pinctrl_probe()
1708 .compatible = "st,stm32mp135-pinctrl",
1715 .compatible = "st,stm32mp157-pinctrl",
1722 .compatible = "st,stm32mp157-z-pinctrl",
1730 .compatible = "st,stm32mp257-pinctrl",
1737 .compatible = "st,stm32mp257-z-pinctrl",
1748 .name = "stm32_gpio-pinctrl",