Lines Matching refs:fmc_d
92 static struct fmc_pdata *fmc_d; variable
96 return io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(controller); in fmc_controller_is_secure()
106 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) in handle_available_semaphores()
109 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in handle_available_semaphores()
114 if (!(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) { in handle_available_semaphores()
115 res = stm32_rif_release_semaphore(fmc_d->base + in handle_available_semaphores()
124 res = stm32_rif_acquire_semaphore(fmc_d->base + in handle_available_semaphores()
143 if (!fmc_d->conf_data) in apply_rif_config()
146 res = clk_enable(fmc_d->fmc_clock); in apply_rif_config()
150 if (fmc_d->is_tdcid) { in apply_rif_config()
152 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) in apply_rif_config()
160 io_clrbits32(fmc_d->base + _FMC_CIDCFGR(i), in apply_rif_config()
170 io_clrsetbits32(fmc_d->base + _FMC_PRIVCFGR, _FMC_PRIVCFGR_MASK, in apply_rif_config()
171 fmc_d->conf_data->priv_conf[0]); in apply_rif_config()
172 io_clrsetbits32(fmc_d->base + _FMC_SECCFGR, _FMC_SECCFGR_MASK, in apply_rif_config()
173 fmc_d->conf_data->sec_conf[0]); in apply_rif_config()
175 if (!fmc_d->is_tdcid) in apply_rif_config()
179 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) in apply_rif_config()
182 io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i), in apply_rif_config()
184 fmc_d->conf_data->cid_confs[i]); in apply_rif_config()
191 io_setbits32(fmc_d->base + _FMC_RCFGLOCKR, in apply_rif_config()
192 fmc_d->conf_data->lock_conf[0]); in apply_rif_config()
200 if ((io_read32(fmc_d->base + _FMC_PRIVCFGR) & in apply_rif_config()
201 fmc_d->conf_data->access_mask[0]) != in apply_rif_config()
202 fmc_d->conf_data->priv_conf[0]) { in apply_rif_config()
207 if ((io_read32(fmc_d->base + _FMC_SECCFGR) & in apply_rif_config()
208 fmc_d->conf_data->access_mask[0]) != in apply_rif_config()
209 fmc_d->conf_data->sec_conf[0]) { in apply_rif_config()
216 clk_disable(fmc_d->fmc_clock); in apply_rif_config()
236 fmc_d->base = io_pa_or_va(&addr, info.reg_size); in parse_dt()
238 res = clk_dt_get_by_index(fdt, node, 0, &fmc_d->fmc_clock); in parse_dt()
243 &fmc_d->pinctrl_d); in parse_dt()
248 &fmc_d->pinctrl_s); in parse_dt()
258 fmc_d->conf_data = calloc(1, sizeof(*fmc_d->conf_data)); in parse_dt()
259 if (!fmc_d->conf_data) in parse_dt()
262 fmc_d->nb_controller = (unsigned int)(lenp / sizeof(uint32_t)); in parse_dt()
263 assert(fmc_d->nb_controller <= FMC_RIF_CONTROLLERS); in parse_dt()
265 fmc_d->conf_data->cid_confs = calloc(FMC_RIF_CONTROLLERS, in parse_dt()
267 fmc_d->conf_data->sec_conf = calloc(1, sizeof(uint32_t)); in parse_dt()
268 fmc_d->conf_data->priv_conf = calloc(1, sizeof(uint32_t)); in parse_dt()
269 fmc_d->conf_data->lock_conf = calloc(1, sizeof(uint32_t)); in parse_dt()
270 fmc_d->conf_data->access_mask = calloc(1, sizeof(uint32_t)); in parse_dt()
271 if (!fmc_d->conf_data->cid_confs || !fmc_d->conf_data->sec_conf || in parse_dt()
272 !fmc_d->conf_data->priv_conf || !fmc_d->conf_data->access_mask) in parse_dt()
275 for (i = 0; i < fmc_d->nb_controller; i++) in parse_dt()
276 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), fmc_d->conf_data, in parse_dt()
295 fmc_d->cclken = true; in parse_dt()
297 if (!fmc_d->cclken) in parse_dt()
302 &fmc_d->clk_period_ns) < 0) in parse_dt()
314 res = clk_enable(fmc_d->fmc_clock); in check_fmc_rif_conf()
323 for (i = 1; i < fmc_d->nb_controller; i++) { in check_fmc_rif_conf()
324 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); in check_fmc_rif_conf()
325 uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i)); in check_fmc_rif_conf()
344 clk_disable(fmc_d->fmc_clock); in check_fmc_rif_conf()
354 if (clk_enable(fmc_d->fmc_clock)) in configure_fmc()
357 semcr = io_read32(fmc_d->base + _FMC_SEMCR(0)); in configure_fmc()
358 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); in configure_fmc()
374 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(0), in configure_fmc()
378 if (fmc_d->pinctrl_d && pinctrl_apply_state(fmc_d->pinctrl_d)) in configure_fmc()
381 if (fmc_d->cclken) { in configure_fmc()
382 unsigned long hclk = clk_get_rate(fmc_d->fmc_clock); in configure_fmc()
384 unsigned long timing = DIV_ROUND_UP(fmc_d->clk_period_ns * 1000, in configure_fmc()
398 io_clrsetbits32(fmc_d->base + _FMC_CFGR, in configure_fmc()
404 io_setbits32(fmc_d->base + _FMC_CFGR, _FMC_CFGR_ENABLE); in configure_fmc()
407 clk_disable(fmc_d->fmc_clock); in configure_fmc()
425 if (clk_enable(fmc_d->fmc_clock)) in fmc_suspend()
428 if (fmc_controller_is_secure(0) && fmc_d->pinctrl_s && in fmc_suspend()
429 pinctrl_apply_state(fmc_d->pinctrl_s)) in fmc_suspend()
433 fmc_d->conf_data->cid_confs[i] = in fmc_suspend()
434 io_read32(fmc_d->base + _FMC_CIDCFGR(i)) & in fmc_suspend()
437 fmc_d->conf_data->priv_conf[0] = in fmc_suspend()
438 io_read32(fmc_d->base + _FMC_PRIVCFGR) & _FMC_PRIVCFGR_MASK; in fmc_suspend()
439 fmc_d->conf_data->sec_conf[0] = in fmc_suspend()
440 io_read32(fmc_d->base + _FMC_SECCFGR) & _FMC_SECCFGR_MASK; in fmc_suspend()
441 fmc_d->conf_data->lock_conf[0] = in fmc_suspend()
442 io_read32(fmc_d->base + _FMC_RCFGLOCKR) & _FMC_RCFGLOCKR_MASK; in fmc_suspend()
443 fmc_d->conf_data->access_mask[0] = in fmc_suspend()
446 clk_disable(fmc_d->fmc_clock); in fmc_suspend()
468 fmc_d = calloc(1, sizeof(*fmc_d)); in fmc_probe()
469 if (!fmc_d) in fmc_probe()
472 res = stm32_rifsc_check_tdcid(&fmc_d->is_tdcid); in fmc_probe()
474 free(fmc_d); in fmc_probe()
489 if (fmc_d->conf_data) { in fmc_probe()
490 free(fmc_d->conf_data->access_mask); in fmc_probe()
491 free(fmc_d->conf_data->cid_confs); in fmc_probe()
492 free(fmc_d->conf_data->priv_conf); in fmc_probe()
493 free(fmc_d->conf_data->sec_conf); in fmc_probe()
495 free(fmc_d->conf_data); in fmc_probe()
496 free(fmc_d); in fmc_probe()