103 	unsigned int i = 0;  in handle_available_semaphores()  local
105 	for (i = 0; i < FMC_RIF_CONTROLLERS; i++) {  in handle_available_semaphores()
106 		if (!(BIT(i) & fmc_d->conf_data->access_mask[0]))  in handle_available_semaphores()
109 		cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i));  in handle_available_semaphores()
114 		if (!(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) {  in handle_available_semaphores()
116 							  _FMC_SEMCR(i),  in handle_available_semaphores()
120 				     i);  in handle_available_semaphores()
125 							  _FMC_SEMCR(i),  in handle_available_semaphores()
129 				     i);  in handle_available_semaphores()
141 	unsigned int i = 0;  in apply_rif_config()  local
151 		for (i = 0; i < FMC_RIF_CONTROLLERS; i++) {  in apply_rif_config()
152 			if (!(BIT(i) & fmc_d->conf_data->access_mask[0]))  in apply_rif_config()
160 			io_clrbits32(fmc_d->base + _FMC_CIDCFGR(i),  in apply_rif_config()
178 	for (i = 0; i < FMC_RIF_CONTROLLERS; i++) {  in apply_rif_config()
179 		if (!(BIT(i) & fmc_d->conf_data->access_mask[0]))  in apply_rif_config()
182 		io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i),  in apply_rif_config()
184 				fmc_d->conf_data->cid_confs[i]);  in apply_rif_config()
227 	unsigned int i = 0;  in parse_dt()  local
275 	for (i = 0; i < fmc_d->nb_controller; i++)  in parse_dt()
276 		stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), fmc_d->conf_data,  in parse_dt()
311 	unsigned int i = 0;  in check_fmc_rif_conf()  local
323 	for (i = 1; i < fmc_d->nb_controller; i++) {  in check_fmc_rif_conf()
324 		uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i));  in check_fmc_rif_conf()
325 		uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i));  in check_fmc_rif_conf()
328 		if (fmc_controller_is_secure(i)) {  in check_fmc_rif_conf()
423 	unsigned int i = 0;  in fmc_suspend()  local
432 	for (i = 0; i < FMC_RIF_CONTROLLERS; i++)  in fmc_suspend()
433 		fmc_d->conf_data->cid_confs[i] =  in fmc_suspend()
434 			io_read32(fmc_d->base + _FMC_CIDCFGR(i)) &  in fmc_suspend()