165 	.mask = gic_op_disable,
647 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);  in gic_it_configure()  local
652 	io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask);  in gic_it_configure()
654 	io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask);  in gic_it_configure()
656 	io_clrbits32(gd->gicd_base + GICD_IGROUPR(idx), mask);  in gic_it_configure()
659 	io_setbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask);  in gic_it_configure()
667 	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);  in gic_it_set_cpu_mask()
676 	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));  in gic_it_set_cpu_mask()
691 	uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG);  in gic_it_set_prio()
696 	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));  in gic_it_set_prio()
726 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);  in gic_it_enable()  local
732 	assert(!(io_read32(base + GICD_IGROUPR(idx)) & mask));  in gic_it_enable()
735 	io_write32(base + GICD_ISENABLER(idx), mask);  in gic_it_enable()
741 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);  in gic_it_disable()  local
746 	assert(!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask));  in gic_it_disable()
749 	io_write32(gd->gicd_base + GICD_ICENABLER(idx), mask);  in gic_it_disable()
755 	uint32_t mask = BIT32(it % NUM_INTS_PER_REG);  in gic_it_set_pending()  local
763 	io_write32(gd->gicd_base + GICD_ISPENDR(idx), mask);  in gic_it_set_pending()
781 	uint64_t mask = SHIFT_U64(mask_id, 24);  in gic_it_raise_sgi()  local
786 		mask |= BIT64(GICC_SGI_IRM_BIT);  in gic_it_raise_sgi()
796 		mask |= SHIFT_U64(mask_aff1, GICC_SGI_AFF1_SHIFT);  in gic_it_raise_sgi()
797 		mask |= SHIFT_U64(mask_aff2, GICC_SGI_AFF2_SHIFT);  in gic_it_raise_sgi()
798 		mask |= SHIFT_U64(mask_aff3, GICC_SGI_AFF3_SHIFT);  in gic_it_raise_sgi()
801 			mask |= BIT32(mpidr & 0xf);  in gic_it_raise_sgi()
807 			mask |= cpu_mask & 0xff;  in gic_it_raise_sgi()
813 		write_icc_asgi1r(mask);  in gic_it_raise_sgi()
815 		write_icc_sgi1r(mask);  in gic_it_raise_sgi()
819 	uint32_t mask = mask_id;  in gic_it_raise_sgi()
823 	mask |= SHIFT_U32(mask_group, GICD_SGIR_NSATT_SHIFT);  in gic_it_raise_sgi()
825 		mask |= SHIFT_U32(GICD_SGIR_TO_OTHER_CPUS,  in gic_it_raise_sgi()
828 		mask |= SHIFT_U32(GICD_SGIR_TO_THIS_CPU,  in gic_it_raise_sgi()
831 		mask |= SHIFT_U32(cpu_mask & 0xff,  in gic_it_raise_sgi()
836 	io_write32(gd->gicd_base + GICD_SGIR, mask);  in gic_it_raise_sgi()
865 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);  in gic_it_is_enabled()  local
868 	return !!(io_read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask);  in gic_it_is_enabled()
874 	uint32_t mask = 1 << (it % NUM_INTS_PER_REG);  in gic_it_get_group()  local
877 	return !!(io_read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask);  in gic_it_get_group()
916 	uint32_t mask = BIT32(it % NUM_INTS_PER_REG);  in gic_spi_release_to_ns()  local
932 	io_write32(gd->gicd_base + GICD_ICPENDR(idx), mask);  in gic_spi_release_to_ns()
934 	io_setbits32(gd->gicd_base + GICD_IGROUPR(idx), mask);  in gic_spi_release_to_ns()
936 	io_clrbits32(gd->gicd_base + GICD_IGROUPMODR(idx), mask);  in gic_spi_release_to_ns()