80 static bool sam9x60_frac_pll_ready(vaddr_t regmap, uint8_t id)  in sam9x60_frac_pll_ready()  argument
82 	return sam9x60_pll_ready(regmap, id);  in sam9x60_frac_pll_ready()
98 	vaddr_t regmap = frac->core.base;  in sam9x60_frac_pll_set()  local
103 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set()
105 	val = io_read32(regmap + AT91_PMC_PLL_CTRL1);  in sam9x60_frac_pll_set()
109 	if (sam9x60_frac_pll_ready(regmap, core->id) &&  in sam9x60_frac_pll_set()
118 	io_write32(regmap + AT91_PMC_PLL_ACR, val);  in sam9x60_frac_pll_set()
120 	io_write32(regmap + AT91_PMC_PLL_CTRL1,  in sam9x60_frac_pll_set()
127 		io_write32(regmap + AT91_PMC_PLL_ACR, val);  in sam9x60_frac_pll_set()
133 		io_write32(regmap + AT91_PMC_PLL_ACR, val);  in sam9x60_frac_pll_set()
138 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set()
142 	io_setbits32(regmap + AT91_PMC_PLL_CTRL0,  in sam9x60_frac_pll_set()
145 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set()
149 	if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_frac_pll_set()
234 	vaddr_t regmap = core->base;  in sam9x60_frac_pll_set_rate_chg()  local
238 		io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set_rate_chg()
241 		io_write32(regmap + AT91_PMC_PLL_CTRL1,  in sam9x60_frac_pll_set_rate_chg()
245 		io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set_rate_chg()
250 		io_setbits32(regmap + AT91_PMC_PLL_CTRL0,  in sam9x60_frac_pll_set_rate_chg()
254 		io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_frac_pll_set_rate_chg()
259 		if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_frac_pll_set_rate_chg()
279 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set_div()  local
283 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_set_div()
286 	io_clrsetbits32(regmap + AT91_PMC_PLL_CTRL0,  in sam9x60_div_pll_set_div()
290 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_set_div()
294 	if (WAIT_PLL_READY_TIMEOUT(regmap, core->id)) {  in sam9x60_div_pll_set_div()
305 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set()  local
309 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_set()
311 	val = io_read32(regmap + AT91_PMC_PLL_CTRL0);  in sam9x60_div_pll_set()
332 	vaddr_t regmap = core->base;  in sam9x60_div_pll_unprepare()  local
334 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_unprepare()
337 	io_clrbits32(regmap + AT91_PMC_PLL_CTRL0, core->layout->endiv_mask);  in sam9x60_div_pll_unprepare()
339 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_unprepare()
372 	vaddr_t regmap = core->base;  in sam9x60_div_pll_set_rate_chg()  local
381 	io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT,  in sam9x60_div_pll_set_rate_chg()
384 	val = io_read32(regmap + AT91_PMC_PLL_CTRL0);  in sam9x60_div_pll_set_rate_chg()