129 	uintptr_t rcc_base;  member
1272 	pdata->rcc_base = stm32_rcc_base();  in stm32_clk_parse_fdt()
1634 	uintptr_t rcc_base = stm32_rcc_base();  in wait_predivsr()  local
1640 		previvsr = rcc_base + RCC_PREDIVSR1;  in wait_predivsr()
1643 		previvsr = rcc_base + RCC_PREDIVSR2;  in wait_predivsr()
1658 	uintptr_t rcc_base = stm32_rcc_base();  in wait_findivsr()  local
1664 		finvivsr = rcc_base + RCC_FINDIVSR1;  in wait_findivsr()
1667 		finvivsr = rcc_base + RCC_FINDIVSR2;  in wait_findivsr()
1682 	uintptr_t rcc_base = stm32_rcc_base();  in wait_xbar_sts()  local
1683 	uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel);  in wait_xbar_sts()
1735 	uintptr_t rcc_base = stm32_rcc_base();  in flexclkgen_config_channel()  local
1740 	io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
1749 	io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
1759 	io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
1763 	io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),  in flexclkgen_config_channel()
2287 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in clk_stm32_flexgen_get_parent()  local
2290 	address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4);  in clk_stm32_flexgen_get_parent()
2297 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in clk_stm32_flexgen_set_parent()  local
2301 	io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel),  in clk_stm32_flexgen_set_parent()
2314 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in clk_stm32_flexgen_get_rate()  local
2320 	prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) &  in clk_stm32_flexgen_get_rate()
2322 	findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) &  in clk_stm32_flexgen_get_rate()
2406 	uintptr_t rcc_base = stm32_rcc_base();  in clk_stm32_flexgen_set_rate()  local
2415 	io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_set_rate()
2425 	io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_set_rate()
2438 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in clk_stm32_flexgen_enable()  local
2464 	io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_enable()
2473 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in clk_stm32_flexgen_disable()  local
2476 	io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),  in clk_stm32_flexgen_disable()
2507 	uintptr_t rcc_base = clk_stm32_get_rcc_base();  in ck_timer_get_rate_ops()  local
2511 	prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK;  in ck_timer_get_rate_ops()
2513 	timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK;  in ck_timer_get_rate_ops()
3567 		vaddr_t reg_offset = pdata->rcc_base + RCC_SEMCR(i);  in handle_available_semaphores()
3574 		cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i));  in handle_available_semaphores()
3579 		if (!(io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &  in handle_available_semaphores()
3616 				io_clrbits32(pdata->rcc_base + RCC_CIDCFGR(i),  in apply_rcc_rif_config()
3627 		io_clrsetbits32(pdata->rcc_base + RCC_PRIVCFGR(index),  in apply_rcc_rif_config()
3630 		io_clrsetbits32(pdata->rcc_base + RCC_SECCFGR(index),  in apply_rcc_rif_config()
3640 			io_clrsetbits32(pdata->rcc_base + RCC_CIDCFGR(i),  in apply_rcc_rif_config()
3646 		io_setbits32(pdata->rcc_base + RCC_RCFGLOCKR(index),  in apply_rcc_rif_config()
3656 			if ((io_read32(pdata->rcc_base + RCC_PRIVCFGR(index)) &  in apply_rcc_rif_config()
3661 			if ((io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &  in apply_rcc_rif_config()
3680 		pdata->conf_data.cid_confs[i] = io_read32(pdata->rcc_base +  in stm32_rcc_rif_pm_suspend()
3684 		pdata->conf_data.priv_conf[i] = io_read32(pdata->rcc_base +  in stm32_rcc_rif_pm_suspend()
3686 		pdata->conf_data.sec_conf[i] = io_read32(pdata->rcc_base +  in stm32_rcc_rif_pm_suspend()
3688 		pdata->conf_data.lock_conf[i] = io_read32(pdata->rcc_base +  in stm32_rcc_rif_pm_suspend()