1431 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()  local
1432 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_stm32_pll_config_output()
1433 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_output()
1434 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_output()
1435 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_config_output()
1436 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_config_output()
1454 		io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in clk_stm32_pll_config_output()
1497 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()  local
1498 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_csg()
1499 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_csg()
1500 	uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;  in clk_stm32_pll_config_csg()
1515 	io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);  in clk_stm32_pll_config_csg()
1579 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_init()  local
1600 		io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in clk_stm32_pll_init()
2154 	uintptr_t pllxcfgr1 = priv->base + offset_base;  in clk_get_pll_fvco()  local
2155 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_get_pll_fvco()
2156 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_get_pll_fvco()
2190 	uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset;  in clk_stm32_pll_get_rate()  local
2191 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_get_rate()
2192 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_get_rate()
2193 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_get_rate()