651 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\  argument
656 		.flags = (_flags),\
2528 #define STM32_OSC(_name, _flags, _gate_id)\  argument
2535 		.flags = (_flags),\
2540 #define STM32_OSC_MSI(_name, _flags, _gate_id)\  argument
2547 		.flags = (_flags),\
2552 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\  argument
2559 		.flags = (_flags),\
2564 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\  argument
2571 		.flags = (_flags),\
2576 #define STM32_PLL1(_name, _flags, _mux_id)\  argument
2583 		.flags = (_flags),\
2588 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\  argument
2597 		.flags = (_flags),\
2602 #define STM32_PLL3(_name, _flags, _reg, _gate_id, _mux_id)\  argument
2611 		.flags = (_flags),\
2616 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\  argument
2625 		.flags = (_flags),\
2658 #define STM32_FLEXGEN(_name, _flags, _flex_id)\  argument
2665 		.flags = (_flags) | CLK_SET_RATE_UNGATE,\
2757 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\  argument
2765 		.flags = (_flags),\