1016 	int subnode = 0;  in stm32_clk_parse_oscillator_fdt()  local
1021 	fdt_for_each_subnode(subnode, fdt, node) {  in stm32_clk_parse_oscillator_fdt()
1026 		cchar = fdt_get_name(fdt, subnode, &ret);  in stm32_clk_parse_oscillator_fdt()
1033 		if (fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED)  in stm32_clk_parse_oscillator_fdt()
1036 		cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);  in stm32_clk_parse_oscillator_fdt()
1042 		if (fdt_getprop(fdt, subnode, "st,bypass", NULL))  in stm32_clk_parse_oscillator_fdt()
1045 		if (fdt_getprop(fdt, subnode, "st,digbypass", NULL))  in stm32_clk_parse_oscillator_fdt()
1048 		if (fdt_getprop(fdt, subnode, "st,css", NULL))  in stm32_clk_parse_oscillator_fdt()
1051 		osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive",  in stm32_clk_parse_oscillator_fdt()
1096 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode,  in clk_stm32_parse_pll_fdt()  argument
1103 	cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);  in clk_stm32_parse_pll_fdt()
1145 		int subnode = 0;  in stm32_clk_parse_fdt_all_pll()  local
1149 		subnode = fdt_subnode_offset(fdt, node, name);  in stm32_clk_parse_fdt_all_pll()
1150 		if (subnode < 0)  in stm32_clk_parse_fdt_all_pll()
1157 		if (clk_stm32_parse_pll_fdt(fdt, subnode, pll))  in stm32_clk_parse_fdt_all_pll()
1168 	int subnode = 0;  in stm32_clk_parse_fdt_opp()  local
1179 	fdt_for_each_subnode(subnode, fdt, node) {  in stm32_clk_parse_fdt_opp()
1182 		if (fdt_read_uint32(fdt, subnode, "hz", &opp_cfg->frq))  in stm32_clk_parse_fdt_opp()
1185 		ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg);  in stm32_clk_parse_fdt_opp()
3698 	int subnode = 0;  in stm32mp21_clk_probe()  local
3706 	fdt_for_each_subnode(subnode, fdt, node) {  in stm32mp21_clk_probe()
3707 		res = dt_driver_maybe_add_probe_node(fdt, subnode);  in stm32mp21_clk_probe()
3710 			     fdt_get_name(fdt, subnode, NULL), res);  in stm32mp21_clk_probe()