1695 					   unsigned int *prediv,  in flexclkgen_search_config()  argument
1704 	assert(clk_src && prediv && findiv);  in flexclkgen_search_config()
1718 			*prediv = (dt_cfg & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;  in flexclkgen_search_config()
1729 				      unsigned int prediv, unsigned int findiv)  in flexclkgen_config_channel()  argument
1737 			RCC_PREDIV0CFGR_PREDIV0_MASK, prediv);  in flexclkgen_config_channel()
2285 	uint32_t prediv = 0;  in clk_stm32_flexgen_get_rate()  local
2290 	prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) &  in clk_stm32_flexgen_get_rate()
2298 	switch (prediv) {  in clk_stm32_flexgen_get_rate()
2315 		EMSG("Unsupported PREDIV value (%#"PRIx32")", prediv);  in clk_stm32_flexgen_get_rate()
2329 						      unsigned int *prediv,  in clk_stm32_flexgen_get_round_rate()  argument
2337 	*prediv = 0;  in clk_stm32_flexgen_get_round_rate()
2361 			*prediv = pre_val[i];  in clk_stm32_flexgen_get_round_rate()
2369 	return (prate / (*prediv + 1)) / (*findiv + 1);  in clk_stm32_flexgen_get_round_rate()
2379 	unsigned int prediv = 0;  in clk_stm32_flexgen_set_rate()  local
2385 	clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv);  in clk_stm32_flexgen_set_rate()
2392 			prediv);  in clk_stm32_flexgen_set_rate()