1413 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_output()  local
1414 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_stm32_pll_config_output()
1415 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_output()
1416 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_output()
1417 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_config_output()
1418 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_config_output()
1436 		io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in clk_stm32_pll_config_output()
1479 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_config_csg()  local
1480 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_stm32_pll_config_csg()
1481 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_config_csg()
1482 	uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;  in clk_stm32_pll_config_csg()
1497 	io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);  in clk_stm32_pll_config_csg()
1575 	uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;  in clk_stm32_pll_init()  local
1596 		io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);  in clk_stm32_pll_init()
2161 	uintptr_t pllxcfgr1 = priv->base + offset_base;  in clk_get_pll_fvco()  local
2162 	uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;  in clk_get_pll_fvco()
2163 	uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;  in clk_get_pll_fvco()
2197 	uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset;  in clk_stm32_pll_get_rate()  local
2198 	uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;  in clk_stm32_pll_get_rate()
2199 	uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;  in clk_stm32_pll_get_rate()
2200 	uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;  in clk_stm32_pll_get_rate()