1537 				struct stm32_pll_dt_cfg *pll_conf)  in clk_stm32_pll1_init()  argument
1539 	int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;  in clk_stm32_pll1_init()
1546 		ret = clk_stm32_pll_set_mux(priv, pll_conf->src);  in clk_stm32_pll1_init()
1548 		ret = clk_stm32_pll_check_mux(priv, pll_conf->src);  in clk_stm32_pll1_init()
1562 	stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV],  in clk_stm32_pll1_init()
1563 				 pll_conf->cfg[REFDIV],  in clk_stm32_pll1_init()
1564 				 pll_conf->cfg[POSTDIV1],  in clk_stm32_pll1_init()
1565 				 pll_conf->cfg[POSTDIV2]);  in clk_stm32_pll1_init()
1572 			       struct stm32_pll_dt_cfg *pll_conf)  in clk_stm32_pll_init()  argument
1581 	if (clk_stm32_pll_set_mux(priv, pll_conf->src))  in clk_stm32_pll_init()
1584 	clk_stm32_pll_config_output(priv, pll, pll_conf->src,  in clk_stm32_pll_init()
1585 				    pll_conf->cfg, pll_conf->frac);  in clk_stm32_pll_init()
1587 	if (pll_conf->csg_enabled) {  in clk_stm32_pll_init()
1588 		clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);  in clk_stm32_pll_init()
1601 	struct stm32_pll_dt_cfg *pll_conf = NULL;  in stm32_clk_pll_configure()  local
1609 		pll_conf = clk_stm32_pll_get_pdata(i);  in stm32_clk_pll_configure()
1611 		if (pll_conf->enabled) {  in stm32_clk_pll_configure()
1617 				clk_stm32_pll1_init(priv, i, pll_conf);  in stm32_clk_pll_configure()
1619 				clk_stm32_pll_init(priv, i, pll_conf);  in stm32_clk_pll_configure()
2130 	struct stm32_pll_dt_cfg *pll_conf = NULL;  in clk_stm32_pll1_set_rate()  local
2137 	pll_conf = &opp->pll_cfg;  in clk_stm32_pll1_set_rate()
2139 	clk_stm32_pll1_init(priv, PLL1_ID, pll_conf);  in clk_stm32_pll1_set_rate()