611 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\  argument
616 		.flags = (_flags),\
2507 #define STM32_OSC(_name, _flags, _gate_id)\  argument
2514 		.flags = (_flags),\
2519 #define STM32_OSC_MSI(_name, _flags, _gate_id)\  argument
2526 		.flags = (_flags),\
2550 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\  argument
2557 		.flags = (_flags),\
2562 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\  argument
2569 		.flags = (_flags),\
2574 #define STM32_PLL1(_name, _flags, _mux_id)\  argument
2581 		.flags = (_flags),\
2586 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\  argument
2595 		.flags = (_flags),\
2600 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\  argument
2609 		.flags = (_flags),\
2614 #define RIF_COMPOSITE(_name, _nb_parents, _parents, _flags,\  argument
2625 		.flags = (_flags),\
2666 #define STM32_FLEXGEN(_name, _flags, _flex_id)\  argument
2673 		.flags = (_flags) | CLK_SET_RATE_UNGATE,\
2765 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\  argument
2773 		.flags = (_flags),\