70 	struct stm32_pll_vco vco;  member
1081 				       struct stm32_pll_vco *vco,  in clk_stm32_pll_compute_cfgr1()  argument
1084 	int sel = (vco->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;  in clk_stm32_pll_compute_cfgr1()
1085 	uint32_t divm = vco->div_mn[PLL_CFG_M];  in clk_stm32_pll_compute_cfgr1()
1086 	uint32_t divn = vco->div_mn[PLL_CFG_N];  in clk_stm32_pll_compute_cfgr1()
1133 	struct stm32_pll_vco *vco = &pll_conf->vco;  in clk_stm32_is_pll_config_on_the_fly()  local
1140 	ret = clk_stm32_pll_compute_cfgr1(pll, vco, &value);  in clk_stm32_is_pll_config_on_the_fly()
1144 	sel = (vco->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;  in clk_stm32_is_pll_config_on_the_fly()
1159 	fracr = vco->frac << RCC_PLLNFRACR_FRACV_SHIFT;  in clk_stm32_is_pll_config_on_the_fly()
1184 				     struct stm32_pll_vco *vco)  in clk_stm32_pll_config_vco()  argument
1189 	if (clk_stm32_pll_compute_cfgr1(pll, vco, &value) != 0) {  in clk_stm32_pll_config_vco()
1202 		   vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);  in clk_stm32_pll_config_vco()
1209 				     struct stm32_pll_vco *vco)  in clk_stm32_pll_config_csg()  argument
1217 	if (!vco->csg_enabled)  in clk_stm32_pll_config_csg()
1220 	mod_per = vco->csg[PLL_CSG_MOD_PER];  in clk_stm32_pll_config_csg()
1221 	inc_step = vco->csg[PLL_CSG_INC_STEP];  in clk_stm32_pll_config_csg()
1222 	sscg_mode = vco->csg[PLL_CSG_SSCG_MODE];  in clk_stm32_pll_config_csg()
1328 		ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);  in clk_stm32_pll_init()
1332 		clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);  in clk_stm32_pll_init()
1337 		clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);  in clk_stm32_pll_init()
1365 		if (pll_conf->vco.status) {  in stm32_clk_pll_configure()
1500 					 struct stm32_pll_vco *vco)  in clk_stm32_load_vco_config_fdt()  argument
1504 	ret = fdt_read_uint32_array(fdt, subnode, "divmn", vco->div_mn,  in clk_stm32_load_vco_config_fdt()
1509 	ret = fdt_read_uint32_array(fdt, subnode, "csg", vco->csg,  in clk_stm32_load_vco_config_fdt()
1512 	vco->csg_enabled = (ret == 0);  in clk_stm32_load_vco_config_fdt()
1520 	vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |  in clk_stm32_load_vco_config_fdt()
1523 	vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);  in clk_stm32_load_vco_config_fdt()
1525 	vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);  in clk_stm32_load_vco_config_fdt()
1561 	err = clk_stm32_load_vco_config_fdt(fdt, subnode_vco, &pll->vco);  in clk_stm32_parse_pll_fdt()
1867 		clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);  in clk_stm32_pll1_set_rate()