1427 	int subnode = 0;  in clk_stm32_parse_oscillator_fdt()  local
1429 	fdt_for_each_subnode(subnode, fdt, node) {  in clk_stm32_parse_oscillator_fdt()
1434 		cchar = fdt_get_name(fdt, subnode, &ret);  in clk_stm32_parse_oscillator_fdt()
1439 		    fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED)  in clk_stm32_parse_oscillator_fdt()
1442 		cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);  in clk_stm32_parse_oscillator_fdt()
1448 		if (fdt_getprop(fdt, subnode, "st,bypass", NULL))  in clk_stm32_parse_oscillator_fdt()
1451 		if (fdt_getprop(fdt, subnode, "st,digbypass", NULL))  in clk_stm32_parse_oscillator_fdt()
1454 		if (fdt_getprop(fdt, subnode, "st,css", NULL))  in clk_stm32_parse_oscillator_fdt()
1457 		osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive",  in clk_stm32_parse_oscillator_fdt()
1499 static int clk_stm32_load_vco_config_fdt(const void *fdt, int subnode,  in clk_stm32_load_vco_config_fdt()  argument
1504 	ret = fdt_read_uint32_array(fdt, subnode, "divmn", vco->div_mn,  in clk_stm32_load_vco_config_fdt()
1509 	ret = fdt_read_uint32_array(fdt, subnode, "csg", vco->csg,  in clk_stm32_load_vco_config_fdt()
1523 	vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);  in clk_stm32_load_vco_config_fdt()
1525 	vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);  in clk_stm32_load_vco_config_fdt()
1530 static int clk_stm32_load_output_config_fdt(const void *fdt, int subnode,  in clk_stm32_load_output_config_fdt()  argument
1533 	return fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr",  in clk_stm32_load_output_config_fdt()
1537 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode,  in clk_stm32_parse_pll_fdt()  argument
1545 	cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);  in clk_stm32_parse_pll_fdt()
1580 		int subnode = 0;  in stm32_clk_parse_fdt_all_pll()  local
1585 		subnode = fdt_subnode_offset(fdt, node, name);  in stm32_clk_parse_fdt_all_pll()
1586 		if (subnode < 0)  in stm32_clk_parse_fdt_all_pll()
1589 		err = clk_stm32_parse_pll_fdt(fdt, subnode, pll);  in stm32_clk_parse_fdt_all_pll()
1601 	int subnode = 0;  in stm32_clk_parse_fdt_opp()  local
1611 	fdt_for_each_subnode(subnode, fdt, node) {  in stm32_clk_parse_fdt_opp()
1617 		opp_cfg->frq = fdt_read_uint32_default(fdt, subnode,  in stm32_clk_parse_fdt_opp()
1621 		opp_cfg->src = fdt_read_uint32_default(fdt, subnode,  in stm32_clk_parse_fdt_opp()
1625 		opp_cfg->div = fdt_read_uint32_default(fdt, subnode,  in stm32_clk_parse_fdt_opp()
1629 		ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg);  in stm32_clk_parse_fdt_opp()