1132 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_is_pll_config_on_the_fly()  local
1151 	if (io_read32(pll_base + RCC_OFFSET_PLLXCFGR1) != value) {  in clk_stm32_is_pll_config_on_the_fly()
1163 	if ((io_read32(pll_base + RCC_OFFSET_PLLXFRACR) == fracr) &&  in clk_stm32_is_pll_config_on_the_fly()
1164 	    (io_read32(pll_base + RCC_OFFSET_PLLXCFGR2) == value)) {  in clk_stm32_is_pll_config_on_the_fly()
1186 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_vco()  local
1195 	io_write32(pll_base + RCC_OFFSET_PLLXCFGR1, value);  in clk_stm32_pll_config_vco()
1198 	io_write32(pll_base + RCC_OFFSET_PLLXFRACR, 0);  in clk_stm32_pll_config_vco()
1201 	io_write32(pll_base + RCC_OFFSET_PLLXFRACR,  in clk_stm32_pll_config_vco()
1204 	io_setbits32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE);  in clk_stm32_pll_config_vco()
1211 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_csg()  local
1231 	io_write32(pll_base + RCC_OFFSET_PLLXCSGR, value);  in clk_stm32_pll_config_csg()
1232 	io_setbits32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL);  in clk_stm32_pll_config_csg()
1239 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_out()  local
1244 	io_write32(pll_base + RCC_OFFSET_PLLXCFGR2, value);  in clk_stm32_pll_config_out()
1717 	uintptr_t pll_base = priv->base + cfg->reg_pllxcr;  in clk_stm32_pll_get_rate()  local
1724 	cfgr1 = io_read32(pll_base + RCC_OFFSET_PLLXCFGR1);  in clk_stm32_pll_get_rate()
1725 	fracr = io_read32(pll_base + RCC_OFFSET_PLLXFRACR);  in clk_stm32_pll_get_rate()
1774 	uintptr_t pll_base = priv->base + cfg->reg_pllxcr;  in clk_stm32_pll_disable()  local
1780 	io_clrbits32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |  in clk_stm32_pll_disable()